Semiconductor processing method for providing large grain polysilicon films

Claim 1

A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprising the following sequential steps: depositing a first layer of arsenic atop the semiconductor wafer to a thickness of less than about 5 Angstroms, the first layer of arsenic deposited at a temperature of greater than about 450 degrees C. and a pressure of about 1 mTorr to about 1 Torr; after depositing the first layer of arsenic, depositing a second layer of amorphous silicon over the first layer of arsenic at a temperature of less than about 585 degrees C. and to a thickness of less than about 2000 Angstroms, the second layer of amorphous silicon having a substantially unoxidized outer surface and a given grain size; after depositing the second layer of amorphous silicon, providing a masking layer atop the exposed unoxidized outer surface of the second layer of amorphous silicon to a thickness effective to substantially prohibit outgasing of the first layer of arsenic; after providing the masking layer, conducting a first annealing of the semiconductor wafer at a temperature of at least about 600 degrees C. for a time period sufficient to encourage diffusion of the first layer of arsenic within the second layer of amorphous silicon and to subsequently increase the size of the grains in the second layer of amorphous silicon during the first annealing step, the amorphous silicon layer crystallizing during the first annealing step into polysilicon; after the first annealing, removing the masking layer thereby exposing the unoxidized outer surface of the second layer of polysilicon; and after removing the masking layer and with the substantially unoxidized outer surface exposed, conducting a second in time annealing of the semiconductor wafer for a time period sufficient to substantially outgas the arsenic from the second layer of polysilicon, the outgasing of the arsenic from the second layer of polysilicon increasing the resistance of the second layer of polysilicon.