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US5242507A Expired / Lapsed US ⏱️ 0.0 years remaining

Impurity-induced seeding of polycrystalline semiconductors

Assignee: Boston University
•
Filing: 1991-05-06
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Granted: 1993-09-07
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Expires: 2011-05-06
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Abstract

Abstract A semiconductor fabrication process improves the crystal structure of a polycrystalline semiconductor. Adding impurities in large quantities causes an acceleration of the crystallization without noticeably increasing the number of spontaneous nucleations in the material. The result is a region of relatively larger crystalline grains within the doped region which extend approximately 1 μm into the undoped region by the time the entire material has crystallized. Junction devices can be created with better electrical characteristics than ordinary polycrystalline semiconductor devices due to fewer grain boundaries at the electrical junctions. One fabrication technique can result in single crystal devices. Another implementation shows a method for fabricating improved polycrystalline vertical diodes such as solar cells.

Inventors

  • 👤 Ralph B. Iverson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 07:20
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0221; H10D86/0223; H10D86/0225; H10F; H10F71/00; H10F71/128; H10F71/131; H10F77/00; H10F77/10; H10F77/16; H10F77/169; H10F77/1692; H10P14/29; H10P14/2901; H10P14/2922; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3451; H10P14/3452; H10P14/3456; Y; Y02; Y02E; Y02E10/00; Y02E10/50; Y02P; Y02P70/00; Y02P70/50

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 56 words
A polycrystalline semiconductor device comprising: a conductivity junction contained within a single crystal grain of a first polycrystalline region of the semiconductor device, the first polycrystalline region having a structure of relatively large crystal grains; and a second polycrystalline region of the semiconductor device, the second polycrystalline region having a structure of relatively small crystal grains.
Claim 2
Dependent Claim 56 words
A polycrystalline semiconductor device comprising: a conductivity junction contained within a single crystal grain of a first polycrystalline region of the semiconductor device, the first polycrystalline region having a structure of relatively large crystal grains; and a second polycrystalline region of the semiconductor device, the second polycrystalline region having a structure of relatively small crystal grains.
Claim 3
Dependent Claim 14 words
A device as claimed in claim 1 wherein said device is a silicon device.
Claim 4
Dependent Claim 26 words
A device as claimed in claim 1 wherein said device is fabricated on a semiconductor body having a substrate lying on a previously fabricated semiconductor body.
Claim 5
Dependent Claim 48 words
A device as claimed in claim 1 wherein said device includes a second conductivity junction within a third crystallized region of said semiconductor device, said third region having a grain structure like that of said first region and being separated from said first region by said second region.
Claim 6
Dependent Claim 80 words
A polycrystalline semiconductor device comprising: a conductivity junction contained within a first crystallized region of said semiconductor device, said first region having a structure of relatively large crystal grains; and a second crystallized region of said semiconductor device bordering said first region, said second region having a structure of relatively small crystal grains, said device being fabricated vertically within a semiconductor layer with said first region above said second region and said conductivity junction existing horizontally within said first region.
Claim 7
Dependent Claim 80 words
A polycrystalline semiconductor device comprising: a conductivity junction contained within a first crystallized region of said semiconductor device, said first region having a structure of relatively large crystal grains; and a second crystallized region of said semiconductor device bordering said first region, said second region having a structure of relatively small crystal grains, said device being fabricated vertically within a semiconductor layer with said first region above said second region and said conductivity junction existing horizontally within said first region.
Claim 8
Independent Claim 154 words
A method of forming a polycrystalline semiconductor body with a controlled grain structure comprising: providing an amorphous semiconductor material on a non-seeding substrate; adding impurities to predetermined discrete regions of the semiconductor material; and heating the semiconductor material to induce spontaneous nucleation throughout the material, the impurities providing a conductivity junction to be part of an active semiconductor device and enhancing the rate of crystallization in the discrete regions such that the spontaneous nucleation crystals of relatively large grain size form in discrete impurity-enhanced regions, spontaneous nucleation crystals of relatively small size form a polycrystalline region of the semiconductor device which has a structure of relatively small crystal grains outside the discrete impurity-enhanced regions, said large grain size crystals extending beyond the discrete impurity-enhanced regions such that the conductivity junction is contained within a single crystal grain of a polycrystalline region of the semiconductor device which has a structure of relatively large crystal grains.
Claim 9
Independent Claim 154 words
A method of forming a polycrystalline semiconductor body with a controlled grain structure comprising: providing an amorphous semiconductor material on a non-seeding substrate; adding impurities to predetermined discrete regions of the semiconductor material; and heating the semiconductor material to induce spontaneous nucleation throughout the material, the impurities providing a conductivity junction to be part of an active semiconductor device and enhancing the rate of crystallization in the discrete regions such that the spontaneous nucleation crystals of relatively large grain size form in discrete impurity-enhanced regions, spontaneous nucleation crystals of relatively small size form a polycrystalline region of the semiconductor device which has a structure of relatively small crystal grains outside the discrete impurity-enhanced regions, said large grain size crystals extending beyond the discrete impurity-enhanced regions such that the conductivity junction is contained within a single crystal grain of a polycrystalline region of the semiconductor device which has a structure of relatively large crystal grains.
Claim 10
Dependent Claim 23 words
A method as claimed in claim 6 wherein said impurities also provide a conductivity junction to be part of an active semiconductor device.
Claim 11
Dependent Claim 15 words
A method as claimed in claim 6 wherein said heating process is a low-temperature process.
Claim 12
Dependent Claim 16 words
A method as claimed in claim 6 wherein said semiconductor is formed on a non-seeding substrate.
Claim 13
Dependent Claim 13 words
A method as claimed in claim 6 wherein said semiconductor material is silicon.
Claim 14
Dependent Claim 22 words
A method as claimed in claim 6 wherein said semiconductor material is deposited in a polycrystalline state and amorphized by ion implantation.
Claim 15
Dependent Claim 12 words
A method as claimed in claim 6 wherein said impurities include phosphorus.
Claim 16
Dependent Claim 12 words
A method as claimed in claim 6 wherein said impurities include arsenic.
Claim 17
Dependent Claim 12 words
A method as claimed in claim 6 wherein said impurities include boron.
Claim 18
Dependent Claim 15 words
A method as claimed in claim 6 wherein said impurities are added by ion implantation.
Claim 19
Dependent Claim 21 words
A method as claimed in claim 6 wherein said impurities are added by diffusion through the surface of said semiconductor material.
Claim 20
Dependent Claim 17 words
A method as claimed in claim 6 wherein said semiconductor material is masked before adding said impurities.

References Cited (Backward Citations)

US4379020A Cited
US4959700A Cited
JPS61119079A Cited
US4693759A Cited
GB2171844A Cited
US4755865A Cited
JPS62214669A Cited
US4762801A Cited
JPS6411369A Cited
US4952526A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-09-06 1997-03-08 1997-09-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-09-06 2001-03-08 2001-09-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-09-06 2005-03-08 2005-09-07 $7700.00 Window Closed / Lapsed

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