Patent US6001697A successfully refreshed from Google Patents.
US6001697A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing semiconductor devices having raised doped regions
Assignee: Promos Technologies Inc
•
Filing: 1998-03-24
•
Granted: 1999-12-14
•
Expires: 2018-03-24
Abstract
Abstract A method of manufacturing a raised source/drain semiconductor device is disclosed. When the shallow junction technique is applied, over etching of the source/drain regions during contact etching and salicide processing will lead to current leakage. The invention provides a method which comprises depositing a buffer conductive layer above the substrate and removing a portion of this layer to form buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions.
Inventors
- 👤 A. J. Chang
- 👤 Chih-Hsun Chu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0212; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
94 words
A method of forming a semiconductor device containing raised doped regions comprising the steps of: a) receiving a semiconductor substrate comprising isolation structures, at least one stack gate structures, a plurality of side-wall spacers, and source/drain regions; b) forming a conductive layer above said substrate; c) depositing a first dielectric layer on said conductive layer; d) applying a first etching process to expose the portion of said conductive layer which is around said stack gate structure; e) applying oxidation process which can transfer the exposed portion of said conductive layer into an oxide material.
Claim 2
Independent Claim
94 words
A method of forming a semiconductor device containing raised doped regions comprising the steps of: a) receiving a semiconductor substrate comprising isolation structures, at least one stack gate structures, a plurality of side-wall spacers, and source/drain regions; b) forming a conductive layer above said substrate; c) depositing a first dielectric layer on said conductive layer; d) applying a first etching process to expose the portion of said conductive layer which is around said stack gate structure; e) applying oxidation process which can transfer the exposed portion of said conductive layer into an oxide material.
Claim 3
Dependent Claim
27 words
A method according to claim 1, after step (e), further comprising steps of: applying masking and defining processes to remove said conductive layer on the isolation structure.
Claim 4
Dependent Claim
19 words
A method according to claim 1, after step (e), further comprising steps of: f) applying a dielectric etching process.
Claim 5
Dependent Claim
24 words
A method according to claim 2, further comprising a step of: g) masking and removing portions of said conductive layer on said isolation structures.
Claim 6
Dependent Claim
18 words
A method according to claim 4, further comprising a step of: h) applying a salicide layer formation process.
Claim 7
Dependent Claim
19 words
A method according to claim 5, further comprising a step of: i) depositing a passivation layer above said substrate.
Claim 8
Dependent Claim
21 words
A method of claim 1, wherein step (b) comprising steps of: b1) depositing a polysilicon layer; b2) applying an ion implantation.
Claim 9
Dependent Claim
19 words
A method according to claim 1, wherein said oxidation process in step (e) is an annealing process with oxygen.
Claim 10
Dependent Claim
14 words
A method of claim 1, wherein said first dielectric layer is a flowable material.
Claim 11
Dependent Claim
13 words
A method of claim 9, wherein said flowable material is SOG (Spin-On Glass).
Claim 12
Dependent Claim
11 words
A method of claim 9, wherein said flowable material is BPSG.
Claim 13
Independent Claim
139 words
A method of forming a semiconductor circuit device having raised doped regions comprising the steps of: a) receiving a semiconductor substrate comprising isolation structures, at least one stack gate structures, a plurality of side-wall spacers, and source/drain regions; b) forming a multiple layer composing with a conductive layer and a nitride layer on said conductive layer; c) depositing a first dielectric layer on said nitride layer; d) applying a first etching process to expose the portion of said conductive layer which is around said stack gate structure; e) applying oxidation process which can transfer the exposed portion of said conductive layer into an oxide material; f) applying a dielectric etching process; g) masking and removing portions of said conductive layer on said isolation structures; h) applying a salicide layer formation process; i) depositing a passivation layer above said substrate.
Claim 14
Independent Claim
139 words
A method of forming a semiconductor circuit device having raised doped regions comprising the steps of: a) receiving a semiconductor substrate comprising isolation structures, at least one stack gate structures, a plurality of side-wall spacers, and source/drain regions; b) forming a multiple layer composing with a conductive layer and a nitride layer on said conductive layer; c) depositing a first dielectric layer on said nitride layer; d) applying a first etching process to expose the portion of said conductive layer which is around said stack gate structure; e) applying oxidation process which can transfer the exposed portion of said conductive layer into an oxide material; f) applying a dielectric etching process; g) masking and removing portions of said conductive layer on said isolation structures; h) applying a salicide layer formation process; i) depositing a passivation layer above said substrate.
Claim 15
Dependent Claim
16 words
A method of claim 12, wherein said nitride layer has a thickness of about 25˜100 Angstroms.
Claim 16
Independent Claim
20 words
A method according to claims 12, wherein said gate dielectric layer has a thickness of about 30 to 100 Angstroms.
Claim 17
Independent Claim
19 words
A method according to claims 12, wherein said gate electrode has a thickness of about 1000 to 3000 Angstroms.
Claim 18
Independent Claim
19 words
A method according to claims 12, wherein said conductive layer has a thickness range around 100 to 500 Angstroms.
Claim 19
Dependent Claim
23 words
A method according to claim 12, wherein said stack gate structure comprising at least one dielectric layer, and at least one gate electrode.
References Cited (Backward Citations)
JPS56147451A
Cited
US4822754A
Cited
US4826782A
Cited
US4844776A
Cited
JPH03218663A
Cited
US5879997A
Cited
US5268330A
Cited
JPH07161832A
Cited
US5593923A
Cited
JPH08162453A
Cited
US5759899A
Cited
US5750437A
Cited
US5827768A
Cited
JPH1168099A
Cited
US5915199A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-13 | 2003-06-14 | 2003-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-13 | 2007-06-14 | 2007-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-13 | 2011-06-14 | 2011-12-14 | $7700.00 | Window Closed / Lapsed |