US5593923A
Expired / Lapsed
US
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Method of fabricating semiconductor device having refractory metal silicide layer on impurity region using damage implant and single step anneal
Assignee: NEC Electronics Corp
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Filing: 1995-05-31
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Granted: 1997-01-14
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Expires: 2015-05-31
Abstract
Abstract A method of producing a semiconductor device having a refractory metal silicide film includes the steps of implanting ions such as silicon into an active region such as drain/source region to form a damage portion therein, depositing a refractory metal on the damage portion, and annealing to form the refractory metal silicide layer. This silicide layer is formed by the refractory metal being reacted with silicon in the damage portion of the active region.
Inventors
- 👤 Tadahiko Horiuchi
- 👤 Takashi Ishigami
- 👤 Hiroyuki Nakamura
- 👤 Tohru Mogami
- 👤 Hitoshi Wakabayashi
- 👤 Takemitsu Kunio
- 👤 Koichiro Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
102 words
A method of fabricating a semiconductor device comprising steps of: implanting ions selected from a group of silicon, germanium, phosphor, arsenic, antimony and boron in a surface portion of a semiconductor region to form an ion-implanted portion at said surface portion of said semiconductor region; depositing on said ion-implanted portion a refractory metal film having thickness that is not smaller than four tenths of a thickness of said ion-implanted portion and not larger than the thickness of said ion-implanted portion; and performing a one-step annealing process in which annealing for reacting said refractory metal film with said ion-implanted portion is performed once.
Claim 2
Independent Claim
102 words
A method of fabricating a semiconductor device comprising steps of: implanting ions selected from a group of silicon, germanium, phosphor, arsenic, antimony and boron in a surface portion of a semiconductor region to form an ion-implanted portion at said surface portion of said semiconductor region; depositing on said ion-implanted portion a refractory metal film having thickness that is not smaller than four tenths of a thickness of said ion-implanted portion and not larger than the thickness of said ion-implanted portion; and performing a one-step annealing process in which annealing for reacting said refractory metal film with said ion-implanted portion is performed once.
Claim 3
Dependent Claim
34 words
The method as claimed in claim 1, wherein said metal film is made of a metal selected from a group consisting of elements belonging to columns IVb, Vb and VIb of the periodic table.
Claim 4
Dependent Claim
18 words
The method as claimed in claim 1, wherein said one-step annealing process is performed in a nitric atmosphere.
Claim 5
Dependent Claim
19 words
The method as claimed in claim 1, wherein said one-step annealing process is performed in an inert gas atmosphere.
Claim 6
Dependent Claim
30 words
The method as claimed in claim 4, wherein said one-step annealing process is performed at a temperature not lower than 750° C. for a period not longer than 60 seconds.
Claim 7
Independent Claim
213 words
A method of fabricating a semiconductor device comprising steps of: forming a gate electrode on a gate insulating film covering a semiconductor substrate; doping impurities into said semiconductor substrate by using said gate electrode as a mask to thereby form first source and drain regions; forming side wall spacers on side surfaces of said gate electrode; doping impurities into said first source and drain regions by using said side wall spacers as a mask to thereby form second source and drain regions having an impurity concentration higher than said first source and drain regions in contact with said first source and drain regions; implanting ions selected from a group of silicon, germanium, phosphor, arsenic, antimony and boron in a surface portion of each of said second source and drain regions to form an ion-implanted portion at said surface portion of each of said second source and drain regions; depositing a refractory metal layer on said ion-implanted portion of each of said second source and drain regions with a thickness in a range of four tenths of a thickness of said ion-implanted portion to one time the thickness of said ion-implanted portion; and reacting said refractory metal layer with said ion-implanted portion by a one-step annealing in which annealing for reacting is performed once.
Claim 8
Independent Claim
213 words
A method of fabricating a semiconductor device comprising steps of: forming a gate electrode on a gate insulating film covering a semiconductor substrate; doping impurities into said semiconductor substrate by using said gate electrode as a mask to thereby form first source and drain regions; forming side wall spacers on side surfaces of said gate electrode; doping impurities into said first source and drain regions by using said side wall spacers as a mask to thereby form second source and drain regions having an impurity concentration higher than said first source and drain regions in contact with said first source and drain regions; implanting ions selected from a group of silicon, germanium, phosphor, arsenic, antimony and boron in a surface portion of each of said second source and drain regions to form an ion-implanted portion at said surface portion of each of said second source and drain regions; depositing a refractory metal layer on said ion-implanted portion of each of said second source and drain regions with a thickness in a range of four tenths of a thickness of said ion-implanted portion to one time the thickness of said ion-implanted portion; and reacting said refractory metal layer with said ion-implanted portion by a one-step annealing in which annealing for reacting is performed once.
Claim 9
Dependent Claim
36 words
The method as claimed in claim 6, wherein each of said second source and drain regions is of an N-type and said ion-implanted portion is formed by ion-implanting one of silicon, germanium, arsenic, phosphor, and antimony.
Claim 10
Dependent Claim
34 words
The method as claimed in claim 6, wherein each of said second source and drain regions is of a P-type and said ion-implanted portion is formed by ion-implanting one of silicon, germanium and boron.
Claim 11
Independent Claim
169 words
A method of fabricating a semiconductor device comprising steps of: forming a polysilicon gate on a gate insulating film covering a silicon substrate; selectively doping impurities into said silicon substrate to form source and drain regions; implanting ions selected from a group of silicon, germanium, phosphor, arsenic, antimony and boron to form an ion-implanted portion in each of said polysilicon gate and said source and drain regions, said ion-implanted region having a first thickness; depositing a refractory metal on said ion-implanted portion of each of said polysilicon gate and said source and drain regions with a second thickness that is in a range of four tenths of said first thickness to one time said first thickness; and reacting said refractory metal with silicon in said polysilicon gate and said source and drain regions by a one-step annealing in which annealing for reacting is performed once, said ion-implanted portion of each of said polysilicon gate and said source and drain regions being thereby converted into a refractory metal silicide layer.
Claim 12
Independent Claim
169 words
A method of fabricating a semiconductor device comprising steps of: forming a polysilicon gate on a gate insulating film covering a silicon substrate; selectively doping impurities into said silicon substrate to form source and drain regions; implanting ions selected from a group of silicon, germanium, phosphor, arsenic, antimony and boron to form an ion-implanted portion in each of said polysilicon gate and said source and drain regions, said ion-implanted region having a first thickness; depositing a refractory metal on said ion-implanted portion of each of said polysilicon gate and said source and drain regions with a second thickness that is in a range of four tenths of said first thickness to one time said first thickness; and reacting said refractory metal with silicon in said polysilicon gate and said source and drain regions by a one-step annealing in which annealing for reacting is performed once, said ion-implanted portion of each of said polysilicon gate and said source and drain regions being thereby converted into a refractory metal silicide layer.
Claim 13
Dependent Claim
23 words
The method as claimed in claim 1, wherein said one-step annealing process is performed at a temperature in a range of 750°-900° C.
Claim 14
Dependent Claim
32 words
The method as claimed in claim 10, wherein a sheet resistance of said refractory metal film having been reacted with said ion-implanted portion, is substantially constant within the range of 750°-900° C.
Claim 15
Dependent Claim
32 words
The method as claimed in claim 10, wherein a sheet resistance of said refractory metal film having been reacted with said ion-implanted portion, is about 10 Ω/□ the range of 750°-900° C.
Claim 16
Dependent Claim
57 words
The method as claimed in claim 10, further comprising a step of providing said refractory metal film having been reacted with said ion-implanted portion, with a width of less than 300 nm, wherein a sheet resistance of said refractory metal film having been reacted with said ion-implanted portion is substantially constant within the range of 750°-900° C.
Claim 17
Dependent Claim
23 words
The method as claimed in claim 6, wherein said one-step annealing process is performed at a temperature in a range of 750°-900° C.
Claim 18
Dependent Claim
32 words
The method as claimed in claim 14, wherein a sheet resistance of said refractory metal layer having been reacted with said ion-implanted portion, is substantially constant within the range of 750°-900° C.
Claim 19
Dependent Claim
33 words
The method as claimed in claim 14, wherein a sheet resistance of said refractory metal layer having been reacted with said ion-implanted portion, is about 10 Ω/□ at the range of 750°-900° C.
Claim 20
Dependent Claim
57 words
The method as claimed in claim 14, further comprising a step of providing said refractory metal layer having been reacted with said ion-implanted portion, with a width of less than 300 nm, wherein a sheet resistance of said refractory metal layer having been reacted with said ion-implanted portion is substantially constant within the range of 750°-900° C.
Claim 21
Dependent Claim
23 words
The method as claimed in claim 9, wherein said one-step annealing process is performed at a temperature in a range of 750°-900° C.
Claim 22
Dependent Claim
27 words
The method as claimed in claim 18, wherein a sheet resistance of said refractory metal silicide layer is about 10 Ω/□ within the range of 750°-900° C.
Claim 23
Dependent Claim
45 words
The method as claimed in claim 18, further comprising a step of providing said refractory metal silicide layer with a width of less than 300 nm, wherein a sheet resistance of said refractory metal silicide layer is substantially constant within the range of 750°-900° C.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |