Method for forming self aligned polysilicon contact

Claim 1

A method of semiconductor integrated circuit manufacturing comprising the steps of: forming insulating regions on a substrate; fabricating gate structures on said substrate between the insulating regions thereby forming regions between said gate structure and said insulating regions, said gate structures having insulating sidewalls, a conducting layer, and an insulating top layer comprising a first material; making polysilicon plugs between said gate structure and said insulating regions; implanting impurities into said plugs; oxidizing the surfaces of said plugs and said first material thereby causing said impurities to diffuse into the substrate to form source/drain regions of a field effect transistor, said sate structure being between said source and said drain regions; patterning to expose at least selected portions of the gate structure; etching to remove both the oxide on top of the first material and said first material, thereby exposing portions of said conducting layer but leaving oxide on top of the polysilicon plugs; and forming an electrical contact to said gate structure, said contact extending over said source/drain regions and extending to said insulating regions.

Claim 2

A method of semiconductor integrated circuit manufacturing comprising the steps of: forming insulating regions on a substrate; fabricating gate structures on said substrate between the insulating regions thereby forming regions between said gate structure and said insulating regions, said gate structures having insulating sidewalls, a conducting layer, and an insulating top layer comprising a first material; making polysilicon plugs between said gate structure and said insulating regions; implanting impurities into said plugs; oxidizing the surfaces of said plugs and said first material thereby causing said impurities to diffuse into the substrate to form source/drain regions of a field effect transistor, said sate structure being between said source and said drain regions; patterning to expose at least selected portions of the gate structure; etching to remove both the oxide on top of the first material and said first material, thereby exposing portions of said conducting layer but leaving oxide on top of the polysilicon plugs; and forming an electrical contact to said gate structure, said contact extending over said source/drain regions and extending to said insulating regions.