EP0145927A1
Expired / Lapsed
EP
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Integrated circuit fet structure
Assignee: International Business Machines Corp
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Filing: 1984-11-06
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Granted: —
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Expires: 2004-11-06
Abstract
Abstract @ A method for making contact to a small area field effect transistor device is described. A monocrystalline semiconductor body (10) having at least a surface region of a first conductivity type is provided with an insulating layer (14) over the surface region. A substantially horizontal first conductive layer (16) is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source (26), drain (28) and gate region of the device is to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped conductive layer (20, 22) of the first conductivity type is formed over the openings having these substantially vertical surfaces and over the insulating and conductive layers. The conformal conductive layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof. The semiconductor body with the layered structure thereon is heated at a suitable temperature to cause the dopant of a second conductivity type to diffuse into the semiconductor body from the conformal conductive layer to form the source (26) and drain (28) regions and a first insulating layer (24) upon the surface of the first conductive layer and the conformal conductive layer. A second insulating layer (36) is formed over the vertical conformal conductive layer. Then a gate dielectric (40) is formed upon the surface of the semiconductor body between the source and drain regions. Electrical contacts (52, 56) are made to the first conductive layer through the first insulator layer (24) which effectively make electrical contact to the source and drain regions via the horizontal conductive layer and the vertical conformal conductive layer.
Inventors
- 👤 Joseph Francis Shepard
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 13:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0273; H10D30/0223; H10D30/0227; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10W; H10W20/00; H10W20/01; H10W20/40; H10W20/41; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
252 words
An integrated circuit field effect transistor structure characterized in that it comprises: a semiconductor body (10) having surface regions thereof isolated from other such regions by a pattern of isolation; narrow width PN junction source (26) and drain (28) regions within at least one of said surface regions and spaced from one another and each having a width dimension substantially that of their electrical contact (22, 22); substantially vertical conformal conductive layers (20, 22) in said electrical contact to each of said PN junction regions (26, 28); a substantially horizontal, patterned conductive layer (16) in electrical contact with an edge of each of said vertical conductive layers (20, 22) and separated from said surface regions by a first electrical insulating layer (14); a second insulating layer (36) covering said conformal conductive layers; said horizontal conductive layer (16) is patterned so as to have separated conductive lines from one another; a third electrical insulating layer (24) over said patterned horizontal conductive layers; a gate dielectric (40) over the channel between said source (26) and drain (28) regions; a gate electrode (50, 54) on said gate dielectric (40) and separated from said vertical conductive layers by said second insulating layer; and an electrical ohmic contact (52, 56) to each of said horizontal conductive layers through openings in said third electrical insulating layer (24) which effectively make electrical contact to said narrow width PN junction source (26) and drain (28) regions through said patterned horizontal conductive layer (16) and said vertical conductive layers (20, 22).
Claim 2
Dependent Claim
252 words
An integrated circuit field effect transistor structure characterized in that it comprises: a semiconductor body (10) having surface regions thereof isolated from other such regions by a pattern of isolation; narrow width PN junction source (26) and drain (28) regions within at least one of said surface regions and spaced from one another and each having a width dimension substantially that of their electrical contact (22, 22); substantially vertical conformal conductive layers (20, 22) in said electrical contact to each of said PN junction regions (26, 28); a substantially horizontal, patterned conductive layer (16) in electrical contact with an edge of each of said vertical conductive layers (20, 22) and separated from said surface regions by a first electrical insulating layer (14); a second insulating layer (36) covering said conformal conductive layers; said horizontal conductive layer (16) is patterned so as to have separated conductive lines from one another; a third electrical insulating layer (24) over said patterned horizontal conductive layers; a gate dielectric (40) over the channel between said source (26) and drain (28) regions; a gate electrode (50, 54) on said gate dielectric (40) and separated from said vertical conductive layers by said second insulating layer; and an electrical ohmic contact (52, 56) to each of said horizontal conductive layers through openings in said third electrical insulating layer (24) which effectively make electrical contact to said narrow width PN junction source (26) and drain (28) regions through said patterned horizontal conductive layer (16) and said vertical conductive layers (20, 22).
Claim 3
Dependent Claim
16 words
The integrated circuit of claim 1 wherein said semiconductor body (10) is composed of monocrystalline silicon.
Claim 4
Dependent Claim
42 words
The integrated circuit of claim 1 wherein said vertical conformal conductive layers (20, 22) are composed of highly doped polycrystalline silicon, said horizontal conductive layer (16) is composed of a refractory metal and said semiconductor body (10) is composed of monocrystalline silicon.
Claim 5
Dependent Claim
44 words
The integrated circuit of claim 1 wherein said vertical conformal conductive layers (20, 22) are composed of a highly doped polycrystalline silicon, said horizontal conductive layer (16) is composed of a refractory metal silicide and said semiconductor body (10) is composed of monocrystalline silicon.
Claim 6
Dependent Claim
29 words
The integrated circuit of claim 1 wherein said semiconductor body (10) is composed of P type monocrystalline silicon and said source (26) and drain (28) regions are N type.
Claim 7
Dependent Claim
16 words
The integrated circuit of claim 1 wherein said insulating layers (14, 24, 36) are silicon dioxide.
Claim 8
Dependent Claim
35 words
The integrated circuit of claim 3 or 4 wherein said electrical contact to said base region is a polycrystalline layer and an aluminium layer, and said electrical contacts to said horizontal conductive layer is aluminium.
Claim 9
Dependent Claim
25 words
The integrated circuit of claim 3 or 4 wherein the minimum thickness of the said vertical conformal conductors is between about 100 and 500 nanometers.
Claim 10
Independent Claim
307 words
A method of forming a small area field effect transistor device and making contact thereto comprising the steps of: providing a monocrystalline semiconductor body (10) whose at least a surface region is of a first conductivity; forming an insulating layer (14) on said surface region; forming a substantially horizontal, patterned first conductive layer (16) over said insulating layer; masking and etching said insulating and first conductive layers to provide openings in said layers to the semiconductor body where the source, drain and gate regions of said device is desired to be formed; said openings have substantially vertical surfaces on the layered structure; forming a conformal highly doped of a second conductivity conductive layer (20, 22) over said openings having said substantially vertical surfaces and over said insulating and patterned conductive layer; etching said conformal conductive layer to substantially remove the horizontal portions of said conformal layer while leaving said openings with a substantially vertical said conformal conductive layer on the sides of said openings; heating said body and said layered structure at a suitable temperature to cause dopant of a second conductivity to diffuse into said body from said conformal conductive layer to form said source (26) and drain (28) regions and a first insulator layer upon the surface of the said first conductive layer (24) and said conformal conductor layer; forming a second insulator layer (36) over said vertical conformal conductive layer; forming a gate dielectric (40) on the surface of said semiconductor body between the said source and drain region; forming a gate conductive layer (50) over said gate dielectric; and forming electrical contacts to said patterned first conductive layer (16) through said first insulator layer (24) which effectively makes electrical contacts to said source (26) and drain (28) regions through said first patterned conductive layer (16) and said vertical conformal conductive layers (20, 22).
Claim 11
Independent Claim
307 words
A method of forming a small area field effect transistor device and making contact thereto comprising the steps of: providing a monocrystalline semiconductor body (10) whose at least a surface region is of a first conductivity; forming an insulating layer (14) on said surface region; forming a substantially horizontal, patterned first conductive layer (16) over said insulating layer; masking and etching said insulating and first conductive layers to provide openings in said layers to the semiconductor body where the source, drain and gate regions of said device is desired to be formed; said openings have substantially vertical surfaces on the layered structure; forming a conformal highly doped of a second conductivity conductive layer (20, 22) over said openings having said substantially vertical surfaces and over said insulating and patterned conductive layer; etching said conformal conductive layer to substantially remove the horizontal portions of said conformal layer while leaving said openings with a substantially vertical said conformal conductive layer on the sides of said openings; heating said body and said layered structure at a suitable temperature to cause dopant of a second conductivity to diffuse into said body from said conformal conductive layer to form said source (26) and drain (28) regions and a first insulator layer upon the surface of the said first conductive layer (24) and said conformal conductor layer; forming a second insulator layer (36) over said vertical conformal conductive layer; forming a gate dielectric (40) on the surface of said semiconductor body between the said source and drain region; forming a gate conductive layer (50) over said gate dielectric; and forming electrical contacts to said patterned first conductive layer (16) through said first insulator layer (24) which effectively makes electrical contacts to said source (26) and drain (28) regions through said first patterned conductive layer (16) and said vertical conformal conductive layers (20, 22).
Claim 12
Dependent Claim
100 words
The method of claim 9 wherein after said heating said body the said first insulator layer is also formed upon the exposed monocrystalline layer, and after said heating an ion implantation of N-type ions are made into the horizontal portions of said first insulator layer, removing the first insulator layer on the exposed said semiconductor surface after the forming of said second insulator, and N- lightly doped drain regions are formed adjacent and contiguous to said source and drain regions by out-diffusion from the remaining first insulator layer on the said semiconductor surface during the said forming a gate dielectric.
Claim 13
Dependent Claim
32 words
The method of claim 9 wherein the minimum thickness of the said vertical conformal conductors is between about 100 to 500 nanometers and the channel width is less than about 1000 nanometers.
References Cited (Backward Citations)
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