Patent US4535511A successfully refreshed from Google Patents.
EP0100897A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for contacting a pn junction region
Assignee: International Business Machines Corp
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Filing: 1983-07-13
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Granted: —
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Expires: 2003-07-13
Abstract
Abstract The method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body utilizes a substantially vertical conformal conductive layer (26) formed over the desired PN junction region (30, 32). The body is heated to a suitable temperature to cause a dopant to diffuse from the vertical conductive layer (26) into the semiconductor body to form the narrow width PN junction region (30, 32). A substantially horizontal conductive layer (22) makes contact to the substantially vertical layer (26) so as to have the horizontal conductive layer (22) in electrical contact to the PN junction region (30, 32). Electrical contacts (34, 36) can be established to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of device that can be made.
Inventors
- 👤 Harsaran Singh Bhatia
- 👤 Satyapal Singh Bhatia
- 👤 Jacob Riseman
- 👤 Emmanuel A. Valsamakis
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 14:50
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
218 words
A method for making contact to one or more narrow width PN junction regions comprising: providing a monocrystalline semiconductor body whose at least surface region (14) is of a first conductivity; forming an insulating layer (20) on said surface region; forming a conductive layer (22) over said insulating layer (20); etching regions of said conductive layer (22) and said insulating layer (20) down to said silicon body (10) to form substantially horizontal surfaces and substantially vertical surfaces on the layered structure; forming a conformal conductive layer over said substantially horizontal surfaces and said substantially vertical surfaces; etching said conformal conductive layer to substantially remove said horizontal layer and to provide a narrow vertical conductive layer (26) upon said substantially vertical surfaces and said silicon body; forming an insulator (28) over said conductive layer (22) and said vertical conformal conductive layer (26); heating said body and said layered structure to a temperature to cause dopant of a second conductivity to.diffuse into said body from said vertical conformal conductive layer (26) to form said narrow width PN junction region (30, 32); and forming an electrical contact (34, 36) to said conductive layer (22) through said insulator (28) which effectively contacts said narrow width PN junction region (30, 32) through said conductive layer (22) and said vertical conformal conductive layer (26).
Claim 2
Independent Claim
218 words
A method for making contact to one or more narrow width PN junction regions comprising: providing a monocrystalline semiconductor body whose at least surface region (14) is of a first conductivity; forming an insulating layer (20) on said surface region; forming a conductive layer (22) over said insulating layer (20); etching regions of said conductive layer (22) and said insulating layer (20) down to said silicon body (10) to form substantially horizontal surfaces and substantially vertical surfaces on the layered structure; forming a conformal conductive layer over said substantially horizontal surfaces and said substantially vertical surfaces; etching said conformal conductive layer to substantially remove said horizontal layer and to provide a narrow vertical conductive layer (26) upon said substantially vertical surfaces and said silicon body; forming an insulator (28) over said conductive layer (22) and said vertical conformal conductive layer (26); heating said body and said layered structure to a temperature to cause dopant of a second conductivity to.diffuse into said body from said vertical conformal conductive layer (26) to form said narrow width PN junction region (30, 32); and forming an electrical contact (34, 36) to said conductive layer (22) through said insulator (28) which effectively contacts said narrow width PN junction region (30, 32) through said conductive layer (22) and said vertical conformal conductive layer (26).
Claim 3
Dependent Claim
70 words
The method of claim 1, wherein said contact is made to PN junction regions of a lateral PNP transistor in a silicon body with a surface region (14) of N type conductivity, said heating step is carried out to cause a dopant of P type conductivity to diffuse into said body to form two-spaced said narrow width PN junction regions (30, 32) as emitter and collector of said lateral transistor.
Claim 4
Dependent Claim
16 words
The method of claim 1 or 2, wherein said etching is by anisotropic reactive ion etching.
Claim 5
Dependent Claim
32 words
The method of claim 1 or 2, wherein said conformal conductive layer and resulting narrow dimensioned vertical conductive layer (26) is formed to a thickness of between about 100 and 1000 nanometers.
Claim 6
Dependent Claim
19 words
The method of claim 1 or 2, wherein said heating step is carried out between about 800 and 1100°C.
Claim 7
Dependent Claim
37 words
The method of claim 1, wherein said first conductivity is N type, said second conductivity is P type in a silicon semiconductor body and said insulating layer (20) and said insulator (28) are formed of silicon dioxide.
Claim 8
Dependent Claim
25 words
The method of claim 1, 2 or 6, wherein said conductive layer (22) and said conformal conductive layer are formed of P+ type polycrystalline silicon.
Claim 9
Dependent Claim
21 words
The method of claim 1 or 2, wherein said electrical contact to said conductive layer (22) is formed of aluminum metallurgy.
Claim 10
Dependent Claim
26 words
The method of claim 2, wherein N+ ions are implanted into the area where said PN junction regions (30, 32) are located to improve transistor gain.
Claim 11
Dependent Claim
26 words
The method of claim 2, wherein said lateral PNP transistor is formed electrically isolated from like transistors and vertical NPN transistors by recessed dielectric isolation (18).
Claim 12
Dependent Claim
153 words
An integrated circuit structure comprising a semiconductor body having at least one surface region (14) thereon isolated from other such regions by a pattern of isolation (18), characterized by a narrow width PN junction region within said surface region (14) having a width dimension substantially that of its electrical contact, a substantially vertical conformal conductive layer (26) in said electrical contact to said PN junction region (30, 32), a substantially horizontal conductive layer (22) in electrical contact with an edge of said vertical conductive layer (26) and separated from said surface region (14) by a first electrical insulating layer (20), a second electrical insulating layer (28) over said horizontal conductive layer (22), and an electrical contact (34, 36) to said horizontal conductive layer (22) through an opening in said second electrical insulating layer (28) which electrically contacts said PN junction region through said horizontal conductive layer (22) and said vertical conductive layer (26).
Claim 13
Dependent Claim
153 words
An integrated circuit structure comprising a semiconductor body having at least one surface region (14) thereon isolated from other such regions by a pattern of isolation (18), characterized by a narrow width PN junction region within said surface region (14) having a width dimension substantially that of its electrical contact, a substantially vertical conformal conductive layer (26) in said electrical contact to said PN junction region (30, 32), a substantially horizontal conductive layer (22) in electrical contact with an edge of said vertical conductive layer (26) and separated from said surface region (14) by a first electrical insulating layer (20), a second electrical insulating layer (28) over said horizontal conductive layer (22), and an electrical contact (34, 36) to said horizontal conductive layer (22) through an opening in said second electrical insulating layer (28) which electrically contacts said PN junction region through said horizontal conductive layer (22) and said vertical conductive layer (26).
Claim 14
Dependent Claim
33 words
The integrated circuit structure of claim 11 or 12, wherein said vertical conductive layer (26) and said horizontal conductive layer (22) are composed of polycrystalline silicon and said semiconductor body is monocrystalline silicon.
Claim 15
Dependent Claim
32 words
The integrated circuit structure of claim 12, wherein said monocrystalline silicon is of N type conductivity at least at its surface and said polycrystalline silicon has P type conductivity or vice versa.
Claim 16
Dependent Claim
49 words
The integrated circuit structure of claim 12, wherein said silicon body is composed of a substrate, preferably of P type conductivity, and an N type epitaxial layer (14) and said narrow width PN junction region is a P type region (30, 32) in said N type epitaxial layer (14).
Claim 17
Dependent Claim
43 words
The integrated circuit structure of claim 14, wherein there are two narrow width P regions (30, 32) within said surface region (14), of which one P region is the emitter and the other P region is the collector of a lateral PNP transistor.
Claim 18
Dependent Claim
32 words
The integrated circuit structure of claim 15, wherein each of said P regions is shaped in the form of a ring (48, 50) with one inside of the other and spaced therefrom.
Claim 19
Dependent Claim
12 words
The integrated circuit structure of claim 16, wherein said ring is rectangular.
Claim 20
Dependent Claim
35 words
The integrated circuit structure of claim 11, wherein said silicon body comprises a P type epitaxial layer and said narrow width PN junction region is a N+ type region in said P type epitaxial layer.
Claim 21
Dependent Claim
28 words
The integrated circuit structure of claim 15, wherein said lateral PNP transistor is electrically isolated from like transistors and vertical NPN transistors by said pattern of isolation (18).
Claim 22
Dependent Claim
29 words
The integrated circuit structure of claims 11 or 12, wherein said electrical contact (34, 36) to said horizontal conductive layer (22) is composed of aluminum or an aluminum alloy.
Claim 23
Dependent Claim
23 words
The integrated circuit structure of claim 11, wherein the thickness of said vertical conductive layer (26) is between about 100 and 1000 nanometers.
References Cited (Backward Citations)
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