Fault tolerant selection of die on wafer

Claim 1

A semiconductor wafer comprising: A. plural integrated circuit dies formed on the wafer, each die having plural bond pads receiving electrical power and ground and sending and receiving functional signals and each die including at least one mode bond pad receiving a mode signal that places the integrated circuit die in one of a functional mode and a bypass mode; B. plural probe area pads formed on the wafer separate from the integrated circuit dies; and C. die selector circuits formed on the wafer separate from the integrated circuit dies and the probe area pads, there being one selector circuit for each die, each die selector circuit including a first I/O terminal, a second I/O terminal, and a mode output, the mode output being connected the mode bond pad of its respective integrated circuit die, the die selector circuits being connected in series via their first and second I/O terminals, the first I/O terminal of the first die selector circuit in the series being connected to a first probe area pad and the second I/O terminal of the last die selector circuit in the series being connected to a second probe area pad.