Individualized prepackage AC performance testing of IC dies on a wafer using DC parametric test patterns

Abstract

Abstract A wafer structure and a method of fabricating and testing IC dies (10) on a wafer (12) are incorporated in a wafer fabrication process which produces IC dies having a selected sensitive AC parameter (L EFF ,β,R). Performance of the sensitive AC parameter generally falls within a first range of variation characteristic of the wafer fabrication process. A test structure or test pattern (TNMOS, TPMOS, TNPN, TR) is formed on substantially every die (10) of the wafer (12) for testing in a DC parametric test at the wafer level sorting stage before scribing and packaging the dies from the wafer. The test structures are constructed for generating test measurements in a DC parameter test reflecting the AC performance of the selected sensitive AC parameter. Substantially every die on the wafer is tested at the wafer level sorting stage using the test structures (TNMOS, TPMOS, TNPN, TR) in a DC parametric test. Those dies of the wafer reflecting AC performance of the selected sensitive AC parameter (L EFF , β, R) within a second range of variation narrower than the first range are selected for packaging. The other dies of the wafer are rejected or sorted for other purposes before packaging for increasing the yield of packaged IC dies meeting AC specifications for AC performance within the narrower second range. The test structures include test NMOS (TNMOS) and test PMOS (TPMOS) transistors for test indication of effective gate length L EFF for CMOS transistors; test NPN transistors (TNPN) for reflecting the amplification factor β for bipolar NPN transistors; and test resistors (TR) for test indication of effective resistance, isolation oxide encroachment, overetch or underetch, etc.

Inventors

• 👤 Susan M. Keown
• 👤 Myron J. Miske

Bibliographic Details