US4896108A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits
Assignee: Nokia Bell Labs
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Filing: 1988-07-25
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Granted: 1990-01-23
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Expires: 2008-07-25
Abstract
Abstract A test circuit is described for measuring the specific contact resistivity r c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.
Inventors
- 👤 William T. Lynch
- 👤 Kwok K. Ng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:38
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277; G; G01; G01R; G01R27/00; G01R27/02; G01R27/14; G01R31/00; G01R31/26; G01R31/27; G01R31/275
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
219 words
A semiconductor integrated circuit wafer including chip circuits and a test circuit located at a major surface of the semiconductor wafer, the test circuit comprising: (a) first, second, and third contact electrodes contacting the major surface of the wafer at first, second, and third mutually spaced-apart areas thereof; (b) first, second, and third mutually spaced-apart diffused regions of the wafer contacted by the first, second, and third contact electrodes, respectively; (c) first and second control electrodes overlying first and second channel regions, respectively, of the major surface, the first channel region situated in the space between the first and second spaced-apart areas, and the second channel region situated in the space between the second and third spaced-apart areas; (d) voltage source means, connected to the first and second control electrodes, for causing first and second inversion layers, respectively, to form at the major surface of the wafer in the first and second channel regions, respectively; (e) current source means, connected to the first or the second contact electrode, for causing a flow of current through the first diffused region, the first inversion layer, and the second diffused region; (f) voltage measuring means, connected across the second and third contact electrodes, for measuring the voltage developed across the second and third contact electrodes in response to the flow of current.
Claim 2
Dependent Claim
219 words
A semiconductor integrated circuit wafer including chip circuits and a test circuit located at a major surface of the semiconductor wafer, the test circuit comprising: (a) first, second, and third contact electrodes contacting the major surface of the wafer at first, second, and third mutually spaced-apart areas thereof; (b) first, second, and third mutually spaced-apart diffused regions of the wafer contacted by the first, second, and third contact electrodes, respectively; (c) first and second control electrodes overlying first and second channel regions, respectively, of the major surface, the first channel region situated in the space between the first and second spaced-apart areas, and the second channel region situated in the space between the second and third spaced-apart areas; (d) voltage source means, connected to the first and second control electrodes, for causing first and second inversion layers, respectively, to form at the major surface of the wafer in the first and second channel regions, respectively; (e) current source means, connected to the first or the second contact electrode, for causing a flow of current through the first diffused region, the first inversion layer, and the second diffused region; (f) voltage measuring means, connected across the second and third contact electrodes, for measuring the voltage developed across the second and third contact electrodes in response to the flow of current.
Claim 3
Dependent Claim
29 words
The integrated circuit wafer of claim 1 in which the first, second, and third diffused regions together with the first and second channel regions have an L shaped configuration.
Claim 4
Dependent Claim
15 words
A semiconductor integrated circuit wafer according to claim 2 in which the semiconductor is silicon.
Claim 5
Dependent Claim
20 words
The integrated circuit wafer of claim 3 in which the first, second, and third contact electrodes are essentially metal silicide.
Claim 6
Dependent Claim
16 words
A semiconductor integrated circuit wafer according to claim 1 in which the semiconductor is essentially silicon.
Claim 7
Dependent Claim
20 words
The integrated circuit wafer of claim 5 in which the first, second, and third contact electrodes are essentially metal silicide.
Claim 8
Dependent Claim
29 words
The integrated circuit wafer of claim 5 in which the first, second, and third diffused regions together with the first and second channel regions have an L shaped configuration.
Claim 9
Dependent Claim
41 words
The integrated circuit wafer of claim 5 in which the first and second control electrodes are first and second gate electrodes, respectively, that are spaced from the first and second channel regions, respectively, by first and second gate insulator layers, respectively.
Claim 10
Dependent Claim
62 words
The integrated circuit wafer of claim 8 in which the first and third contact electrodes extend laterally from sidewall insulating layers on the first and second gate electrodes, respectively, to sidewall insulating layers located on edges of a field insulator layer, and in which the second contact electrode extends laterally between sidewall insulating layers located on the first and second gate electrodes.
Claim 11
Dependent Claim
29 words
The integrated circuit wafer of claim 9 in which the first, second, and third diffused regions together with the first and second channel regions have an L shaped configuration.
Claim 12
Dependent Claim
20 words
The integrated circuit wafer of claim 9 in which the first, second, and third contact electrodes are essentially metal silicide.
Claim 13
Dependent Claim
29 words
The integrated circuit wafer of claim 11 in which the first, second, and third diffused regions together with the first and second channel regions have a L shaped configuration.
Claim 14
Dependent Claim
62 words
The integrated circuit wafer of claim 9 in which the first and third contact electrodes extend laterally from sidewall insulating layers on the first and second gate electrodes, respectively, to sidewall insulating layers located on edges of a field insulator layer, and in which the second contact electrode extends laterally between sidewall insulating layers located on the first and second gate electrodes.
Claim 15
Dependent Claim
29 words
The integrated circuit wafer of claim 13 in which the first, second, and third diffused regions together with the first and second channel regions have an L shaped configuration.
Claim 16
Dependent Claim
40 words
The integrated circuit of claim 9 in which the first gate electrode, the first and second contact electrodes, and the first and second diffused regions form a transistor structure that is identical to a transistor structure of the chip circuits.
Claim 17
Dependent Claim
26 words
The integrated circuit wafer of claim 9 in which the first, second, and third diffused regions, respectively, include the first, second and third mutually spaced-apart areas.
Claim 18
Dependent Claim
44 words
The integrated circuit wafer of claim 1 in which the chip circuits comprise a plurality of transistors mutually having the same structure as the transistor formed by the first control electrode, the first and second contact electrodes, and the first and second diffused regions.
Claim 19
Dependent Claim
26 words
The integrated circuit wafer of claim 1 in which the first, second, and third diffused regions, respectively, include the first, second and third mutually spaced-apart areas.
Claim 20
Dependent Claim
219 words
A semiconductor MOS integrated circuit wafer including chip circuits and a test circuit, located at a major surface of the semiconductor wafer, the test circuit comprising: (a) first, second, and third contact electrodes contacting the major surface of the wafer at first, second, and third mutually spaced-apart areas thereof; (b) first, second, and third mutually spaced-apart diffused regions of the wafer contacted by the first, and third contact electrodes respectively; (c) first and second control electrodes overlying first and second channel regions, respectively, of the major surface, the first channel region situated in the space between the first and second spaced-apart areas, and the second channel region situated in the space between the second and third spaced-apart areas; (d) voltage source means, connected to the first and second control electrodes, for causing first and second inversion layers, respectively, to form at the major surface of the wafer in the first and second channel regions, respectively; (e) current source means, connected to the first or the second contact electrode, for causing a flow of current through the first diffused region, the first inversion layer, and the second diffused region; (f) voltage measuring means, connected across the second and third contact electrodes, for measuring the voltage developed across the second and third contact electrodes in response to the flow of current.
Claim 21
Dependent Claim
219 words
A semiconductor MOS integrated circuit wafer including chip circuits and a test circuit, located at a major surface of the semiconductor wafer, the test circuit comprising: (a) first, second, and third contact electrodes contacting the major surface of the wafer at first, second, and third mutually spaced-apart areas thereof; (b) first, second, and third mutually spaced-apart diffused regions of the wafer contacted by the first, and third contact electrodes respectively; (c) first and second control electrodes overlying first and second channel regions, respectively, of the major surface, the first channel region situated in the space between the first and second spaced-apart areas, and the second channel region situated in the space between the second and third spaced-apart areas; (d) voltage source means, connected to the first and second control electrodes, for causing first and second inversion layers, respectively, to form at the major surface of the wafer in the first and second channel regions, respectively; (e) current source means, connected to the first or the second contact electrode, for causing a flow of current through the first diffused region, the first inversion layer, and the second diffused region; (f) voltage measuring means, connected across the second and third contact electrodes, for measuring the voltage developed across the second and third contact electrodes in response to the flow of current.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-22 | 1993-07-24 | 1994-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-22 | 1997-07-24 | 1998-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-22 | 2001-07-24 | 2002-01-23 | $7700.00 | Window Closed / Lapsed |