US4875002A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of testing semiconductor wafers
Assignee: Sharp Corp
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Filing: 1987-11-24
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Granted: 1989-10-17
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Expires: 2007-11-24
Abstract
Abstract Semiconductor wafers are tested more efficiently with an improved throughput. Since a plurality of test items are involved but some tests discover more defects than the others, and since neighboring wafers may be believed to have similar characteristics regarding defects, a spot-checking routine and a preferred sequence in which the plurality of tests are conducted may be selected from the data collected and stored from a preliminary testing so that defective samples are more efficiently identified.
Inventors
- 👤 Hideo Sakamoto
- 👤 Hiroshi Tsugita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:12
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; G; G01; G01R; G01R31/00; G01R31/28; G01R31/316
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
74 words
A method of testing wafers with many chips thereon comprising the steps of conducting tests of a plurality of kinds on chips on said wafers during a predetermined initial period, counting the number of wafers which failed in each of said plurality of kinds of tests, storing said numbers, and automatically selecting one or more of said plurality of kinds of tests for subsequent testing of wafers on the basis of said stored numbers.
Claim 2
Independent Claim
74 words
A method of testing wafers with many chips thereon comprising the steps of conducting tests of a plurality of kinds on chips on said wafers during a predetermined initial period, counting the number of wafers which failed in each of said plurality of kinds of tests, storing said numbers, and automatically selecting one or more of said plurality of kinds of tests for subsequent testing of wafers on the basis of said stored numbers.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said plurality of tests are conducted during said predetermined initial period in a predetermined sequence.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein said plurality of tests are conducted at specified positions of said wafers.
Claim 5
Independent Claim
93 words
A method of testing chips on semiconductor wafers comprising the steps of performing a spot-checking test on every nth one of said chips, n being a preselected integer greater than 1, generating either a "good" or a "bad" signal according to whether the result of said test was satisfactory or not satisfactory, respectively, resuming said spot-checking test step if a "good" signal is generated, and stopping said spot-checking test step if a "bad" signal is generated and immediately thereupon testing m successive chips which follow, m being another preselected integer greater than 1.
Claim 6
Independent Claim
93 words
A method of testing chips on semiconductor wafers comprising the steps of performing a spot-checking test on every nth one of said chips, n being a preselected integer greater than 1, generating either a "good" or a "bad" signal according to whether the result of said test was satisfactory or not satisfactory, respectively, resuming said spot-checking test step if a "good" signal is generated, and stopping said spot-checking test step if a "bad" signal is generated and immediately thereupon testing m successive chips which follow, m being another preselected integer greater than 1.
Claim 7
Dependent Claim
11 words
The method of claim 4 wherein m is greater than n.
Claim 8
Independent Claim
101 words
A method of testing wafers comprising the steps of obtaining data on defects discovered by a plurality of tests conducted in a sequence on chips at specified positions on a wafer, said data being classified according to said positions of said chips on said wafer, storing said data in a memory means, and causing said sequence of said plurality of tests on another chip to be changed according to said data in such a way that a test which discovers defects more frequently at the position of said another chip is conducted with high priority, whereby defective chips are injected efficiently.
Claim 9
Independent Claim
101 words
A method of testing wafers comprising the steps of obtaining data on defects discovered by a plurality of tests conducted in a sequence on chips at specified positions on a wafer, said data being classified according to said positions of said chips on said wafer, storing said data in a memory means, and causing said sequence of said plurality of tests on another chip to be changed according to said data in such a way that a test which discovers defects more frequently at the position of said another chip is conducted with high priority, whereby defective chips are injected efficiently.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |