US4710932A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of and apparatus for fault detection in digital circuits by comparison of test signals applied to a test circuit and a faultless reference circuit
Assignee: Individual
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Filing: 1986-01-15
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Granted: 1987-12-01
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Expires: 2006-01-15
Abstract
Abstract A fault detection system for electronic circuits is disclosed which comprises a detection circuit in which the crosscorrelation values between the test signal sequence, input to a circuit to be tested, and the output signal sequence from it, with no delay and with delays made in steps to a predetermined time interveral either in the test input signal or in the output sequence, are counted, a reference circuit in which the crosscorrelation values between the test signal sequence input to a faultless reference circuit and the output signal sequence from it, are counted, and a comparator for comparing the crosscorrelation values from both the detection and reference circuit. In one preferred embodiment, one or more of the conventional data compression methods selected from the group of the one's counting, transistion counting, auto-correlation, and C. R. C. methods are incorporated for operation in conjunction with the system.
Inventors
- 👤 Kashiwagi Hiroshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:32
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
198 words
An apparatus for fault detection in electronic circuits employing a correlation method, comprising: first test circuitry including a signal generator for supplying a circuit to be tested with a sequence of test signals, at least one delay circuit connected to the output of said generator, a plurality of correlation counters connected to the output of said generator, the output of said delay circuit and the output of said test circuit for counting correlation values between signals input to and output from said tested circuit, a reference circuitry including a second signal generator for supplying a reference faultless circuit with a sequence of test signals, the same number of delay circuits as in said test circuitry connected to the output of said second signal generator, the same number of correlation counters as in said test circuitry connected to the output of said second signal generator and each of the outputs of said delay circuits, and an output of said reference circuit for counting correlation values between the signals input to and output from said reference circuitry, and a comparator connected to outputs of said counters of both said test and reference circuitries for comparing the correlation values output therefrom.
Claim 2
Independent Claim
198 words
An apparatus for fault detection in electronic circuits employing a correlation method, comprising: first test circuitry including a signal generator for supplying a circuit to be tested with a sequence of test signals, at least one delay circuit connected to the output of said generator, a plurality of correlation counters connected to the output of said generator, the output of said delay circuit and the output of said test circuit for counting correlation values between signals input to and output from said tested circuit, a reference circuitry including a second signal generator for supplying a reference faultless circuit with a sequence of test signals, the same number of delay circuits as in said test circuitry connected to the output of said second signal generator, the same number of correlation counters as in said test circuitry connected to the output of said second signal generator and each of the outputs of said delay circuits, and an output of said reference circuit for counting correlation values between the signals input to and output from said reference circuitry, and a comparator connected to outputs of said counters of both said test and reference circuitries for comparing the correlation values output therefrom.
Claim 3
Independent Claim
200 words
An apparatus for fault detection in electronic circuits employing a correlation method, comprising: a first test circuitry including a signal generator for supplying a circuit to be tested with a sequence of test signals, at least one delay circuit connected to the output of said test circuit, a plurality of correlation counters connected to the output of said generator, the output of said delay circuit, and the output of said test circuit for counting the correlation values between the signals input to and output from said test circuit, a reference circuitry including a second signal generator for supplying a reference faultless circuit with a sequence of test signals, the same number of delay circuits as in said test circuitry connected to the output of said reference circuitry, the same number of correlation counters as in said test circuitry connected to the output of said reference circuit and each of the outputs of said delay circuits, and the output of said second signal generator counts correlation values between the signals input to and output from said reference circuitry, and a comparator connected to outputs of said counters of both said test and reference circuitries for comparing the correlation values output therefrom.
Claim 4
Independent Claim
200 words
An apparatus for fault detection in electronic circuits employing a correlation method, comprising: a first test circuitry including a signal generator for supplying a circuit to be tested with a sequence of test signals, at least one delay circuit connected to the output of said test circuit, a plurality of correlation counters connected to the output of said generator, the output of said delay circuit, and the output of said test circuit for counting the correlation values between the signals input to and output from said test circuit, a reference circuitry including a second signal generator for supplying a reference faultless circuit with a sequence of test signals, the same number of delay circuits as in said test circuitry connected to the output of said reference circuitry, the same number of correlation counters as in said test circuitry connected to the output of said reference circuit and each of the outputs of said delay circuits, and the output of said second signal generator counts correlation values between the signals input to and output from said reference circuitry, and a comparator connected to outputs of said counters of both said test and reference circuitries for comparing the correlation values output therefrom.
Claim 5
Dependent Claim
58 words
The apparatus set forth in claim 1 or 2, wherein each of said test and reference circuitries each has a data compression circuit according to at least one data compression methods selected from the group of one's counting, transition counting, auto-correlation, and C. R. C. methods and connected to the outputs of said tested and reference circuits, respectively.
Claim 6
Dependent Claim
153 words
A fault detection method using correlation for electronic circuits, comprising the steps of: inputting a test signal sequence to a circuit to be tested; producing a first output signal sequence from said circuit to be tested. delaying one of said test signal sequence and said first output sequence to produce a delayed sequence; counting first correlation values between the other of said test signal sequence and said first output signal sequence, and said first delayed sequence; inputting said test signal sequence to a reference faultless circuit; producing a second output signal sequence from said reference faultless circuit in response to said test signal sequence; delaying one of said test signal sequence and said second output signal sequence to produce a second delayed sequence; counting correlation values between the other of said test signal sequence and said second output signal sequence, and said second delayed sequence; and comparing said first and second correlation values.
Claim 7
Dependent Claim
153 words
A fault detection method using correlation for electronic circuits, comprising the steps of: inputting a test signal sequence to a circuit to be tested; producing a first output signal sequence from said circuit to be tested. delaying one of said test signal sequence and said first output sequence to produce a delayed sequence; counting first correlation values between the other of said test signal sequence and said first output signal sequence, and said first delayed sequence; inputting said test signal sequence to a reference faultless circuit; producing a second output signal sequence from said reference faultless circuit in response to said test signal sequence; delaying one of said test signal sequence and said second output signal sequence to produce a second delayed sequence; counting correlation values between the other of said test signal sequence and said second output signal sequence, and said second delayed sequence; and comparing said first and second correlation values.
Claim 8
Dependent Claim
50 words
The fault detection method set forth in claim 4, wherein additional comparison is made between the output signals from both said tested and reference circuits by data compression using at least one data compression method selected from the group of one's counting, transition counting, auto-correlation, and C. R. C. methods.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-30 | 1991-06-01 | 1991-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-30 | 1995-06-01 | 1995-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-30 | 1999-06-01 | 1999-12-01 | $7700.00 | Window Closed / Lapsed |