Firmware simulation of diskette data via a video signal

Claim 1

A data processing system including apparatus for verifying the integrity of the system by using a cathode ray tube (CRT) subsystem to generate a stream of data bits to simulate the flow of information between a disk and a disk controller comprising: data random access memory (RAM) means for storing data bytes having a fixed format, each of said data bytes being represented by combinations of clock bit cells, data bit cells and no bit cells, each of said clock bit cells being represented by a first plurality of data bytes, each of said data bit cells being represented by a second plurality of data bytes and each of said no bit cells being represented by a third plurality of data bytes, each of said first, second and third plurality of data bytes being stored in a first predetermined number of locations; CRT controller means for generating a plurality of sequential data RAM address signals and a plurality of raster signals, said data RAM means having means for receiving each of said plurality of sequential data RAM address signals and generating data byte signals representative of the contents of each addressed location of said data RAM means; and character generator RAM means coupled to said data RAM means and said CRT controller means for storing a first byte in a first location, a second byte in a second location and a third byte in a third location, and having means for receiving a sequence of said data byte signals and said plurality of raster signals for addressing combinations of the contents of said first, said second and said third locations and having means for generating said stream of data bits at a first bit rate including said clock bit cells, said data bit cells and said no bit cells representative of said data bytes having said fixed format.