US4327408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controller device with diagnostic capability for use in interfacing a central processing unit with a peripheral storage device
Assignee: EMC Corp
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Filing: 1979-04-17
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Granted: 1982-04-27
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Expires: 1999-04-17
Abstract
Abstract A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral storage device includes a sequencer, a buffer, a microprocessor and various error detection logic. A gate is coupled between the sequencer and the input of the peripheral storage device for enabling or disabling the transfer of data from the sequencer to the peripheral storage device and a multiplexer is coupled between the microprocessor, the output of the peripheral storage device and the sequencer for selecting inputs to the sequencer from either the microprocessor or the peripheral storage device. During a normal write operation, write signals are sent from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device through the gate. During a normal read operation, read signals are sent from the peripheral storage device to the sequencer through the multiplexer and then from the sequencer to the CPU through the buffer. During a test write operation, the input to the peripheral storage device is disabled and write signals that would normally be sent from the sequencer to the peripheral storage device are sent to the microprocessor and then from the microprocessor to the CPU. During a test read operation, simulated read signals are generated in the microprocessor, sent from the microprocessor to the sequencer through the multiplexer and then sent from the sequencer to the CPU through the buffer.
Inventors
- 👤 John M. Frissell
- 👤 Kris E. Swanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2221; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
319 words
In a controller for interfacing a central processor unit to a peripheral storage device, said controller including a sequencer coupled between said central processor unit and said peripheral storage device for controlling the transfer of data between said central processor unit and said peripheral storage device and further including a microprocessor coupled to said central processor unit and said sequencer for controlling said sequencer on commands from the central processor unit, said sequencer including error detecting logic, the improvement comprising circuitry for enabling said controller to be tested for proper operation independent of said peripheral storage device, said circuitry including: a. gating means coupled in the data path between said sequencer and said peripheral storage device and connected to said microprocessor for enabling or disabling the transfer of data to said peripheral storage device from said sequencer in response to commands from the central processor unit so as to place the controller either in a diagnostic mode or a normal operating mode, b. means coupled to said microprocessor, said peripheral storage device and said sequencer for selecting output data from either said microprocessor or said peripheral storage device and transferring said output data to said sequencer on commands from the central processor unit for processing, and c. means coupled between said microprocessor and said sequencer for transferring data from said sequencer to said microprocessor on commands from the central processor unit when said controller is in a diagnostic mode, said data representing control signals generated during normal operation of said sequencer, said microprocessor transferring said data to said central processor unit on command signals from said central processor unit for comparison with expected data, d. whereby, said peripheral storage device may be electrically disconnected from said sequencer and test signals sent to said sequencer from said microprocessor and to said microprocessor from said sequencer, allowing thereby said error detecting logic in said sequencer to be tested for proper operation.
Claim 2
Dependent Claim
319 words
In a controller for interfacing a central processor unit to a peripheral storage device, said controller including a sequencer coupled between said central processor unit and said peripheral storage device for controlling the transfer of data between said central processor unit and said peripheral storage device and further including a microprocessor coupled to said central processor unit and said sequencer for controlling said sequencer on commands from the central processor unit, said sequencer including error detecting logic, the improvement comprising circuitry for enabling said controller to be tested for proper operation independent of said peripheral storage device, said circuitry including: a. gating means coupled in the data path between said sequencer and said peripheral storage device and connected to said microprocessor for enabling or disabling the transfer of data to said peripheral storage device from said sequencer in response to commands from the central processor unit so as to place the controller either in a diagnostic mode or a normal operating mode, b. means coupled to said microprocessor, said peripheral storage device and said sequencer for selecting output data from either said microprocessor or said peripheral storage device and transferring said output data to said sequencer on commands from the central processor unit for processing, and c. means coupled between said microprocessor and said sequencer for transferring data from said sequencer to said microprocessor on commands from the central processor unit when said controller is in a diagnostic mode, said data representing control signals generated during normal operation of said sequencer, said microprocessor transferring said data to said central processor unit on command signals from said central processor unit for comparison with expected data, d. whereby, said peripheral storage device may be electrically disconnected from said sequencer and test signals sent to said sequencer from said microprocessor and to said microprocessor from said sequencer, allowing thereby said error detecting logic in said sequencer to be tested for proper operation.
Claim 3
Dependent Claim
37 words
The improvement in accordance with claim 1 and wherein said means for enabling or disabling the transfer of data to said peripheral storage device comprises a gating unit coupled between said sequencer and said peripheral storage device.
Claim 4
Dependent Claim
16 words
The improvement in accordance with claim 2 and wherein said gating unit comprises an AND gate.
Claim 5
Dependent Claim
59 words
The improvement in accordance with claim 2 and wherein said means for selecting output data from either said microprocessor or said peripheral storage device and transferring such data to said sequencer comprises a multiplexer having an input port connected to said microprocessor, an input port connected to said peripheral storage device and an output port connected to said sequencer.
Claim 6
Dependent Claim
24 words
The improvement in accordance with claim 4 and wherein said means for transferring data from said sequencer to said microprocessor comprises a data bus.
Claim 7
Dependent Claim
54 words
The improvement of claim 5 and wherein said controller further includes a buffer connected between said central processor unit and said sequencer and coupled to said microprocessor for providing temporary storage of data transferred to and from said central processor unit that would either be stored on or read from said peripheral storage device.
Claim 8
Independent Claim
144 words
A method of testing the operation of a controller, said controller interfacing a central processor unit to a peripheral storage device, said controller including a sequencer coupled between said central processor unit and said peripheral storage device for controlling the transfer of data to and from said peripheral storage device and a microprocessor coupled to said sequencer for controlling the operation of said sequencer, the method comprising: a. deactivating all control lines to said peripheral storage device from said controller, and b. sending test data from said central processor unit to said controller and then from said controller back to said central processor unit along a path which includes said sequencer, c. whereby said microprocessor can simulate signals, including false signals that would normally come from said peripheral storage device, and transmit said signals to said sequencer for the purpose of testing said sequencer.
Claim 9
Independent Claim
144 words
A method of testing the operation of a controller, said controller interfacing a central processor unit to a peripheral storage device, said controller including a sequencer coupled between said central processor unit and said peripheral storage device for controlling the transfer of data to and from said peripheral storage device and a microprocessor coupled to said sequencer for controlling the operation of said sequencer, the method comprising: a. deactivating all control lines to said peripheral storage device from said controller, and b. sending test data from said central processor unit to said controller and then from said controller back to said central processor unit along a path which includes said sequencer, c. whereby said microprocessor can simulate signals, including false signals that would normally come from said peripheral storage device, and transmit said signals to said sequencer for the purpose of testing said sequencer.
Claim 10
Dependent Claim
93 words
The method of claim 7 and wherein said test data sent from said central processor unit to said controller and then back to said central processor unit comprises test write signals which are sent from said central processor unit to said sequencer, then from said sequencer to said microprocessor and then from said microprocessor to said central processor unit, said sequencer interpreting said data signals as if they were coming from said central processor unit whereby said central processor unit can examine data that would normally be supplied to said peripheral storage device.
Claim 11
Dependent Claim
65 words
The method of claim 7 and wherein said test data sent from said central processor unit to said controller and then back to said central processor unit comprise test read signals which are generated in said microprocessor and sent to the sequencer and then sent to the central processing unit can examine data simulating data that would normally be coming from said central processor unit.
Claim 12
Dependent Claim
48 words
The method of claim 9 and wherein said test read signals comprise pulse signals generated in said microprocessor simulating at least some of the signals sent from said peripheral storage device to said controller during a read operation, which signals can be examined by said central processor unit.
Claim 13
Dependent Claim
28 words
The method of claim 10 and wherein said pulse signals are transferred from said microprocessor to said sequencer and then from said sequencer to said central processor unit.
Claim 14
Dependent Claim
189 words
A data processing system comprising: a. a central processor unit for processing data, b. a peripheral storage device having an input and an output for storing data, and c. further including a controller coupled between said central processor unit and said peripheral storage device for interfacing said central processor unit to said peripheral storage device for the purpose of allowing data to be moved between said central processor unit and said peripheral storage device, said controller comprising: 1. a sequencer unit coupled to said central processor unit and said peripheral storage device for controlling the transfer of data to and from said central processor unit, 2. a microcomputer unit coupled to said central processor unit and said sequencer unit for controlling the operations of said controller, 3. gating means connected to said micro-computer unit, 4. data transfer bus means connecting said sequencer unit to said gating means, 5. data transfer bus means connecting said gating means to the input of said peripheral storage device, said gating means enabling or disabling the transfer of data between said sequencer unit and said peripheral storage device on signals from said microcomputer unit,
Claim 15
Dependent Claim
189 words
A data processing system comprising: a. a central processor unit for processing data, b. a peripheral storage device having an input and an output for storing data, and c. further including a controller coupled between said central processor unit and said peripheral storage device for interfacing said central processor unit to said peripheral storage device for the purpose of allowing data to be moved between said central processor unit and said peripheral storage device, said controller comprising: 1. a sequencer unit coupled to said central processor unit and said peripheral storage device for controlling the transfer of data to and from said central processor unit, 2. a microcomputer unit coupled to said central processor unit and said sequencer unit for controlling the operations of said controller, 3. gating means connected to said micro-computer unit, 4. data transfer bus means connecting said sequencer unit to said gating means, 5. data transfer bus means connecting said gating means to the input of said peripheral storage device, said gating means enabling or disabling the transfer of data between said sequencer unit and said peripheral storage device on signals from said microcomputer unit,
Claim 16
Dependent Claim
263 words
multiplexer means having an output connected to said sequencer unit, an input connected to said microprocessor and an input connected to the output of said peripheral storage device for transferring data to said sequencer unit from either said microcomputer unit or said peripheral storage device, 7. data transfer bus means connecting said sequencer unit to said microcomputer for enabling data signals sent to said sequencer unit to be transmitted to said microcomputer unit, 8. data transfer means connecting said central processor unit to said sequencer unit for enabling data signals to be sent between said central processor unit and said sequencer unit, 9. data transfer bus means connecting said microcomputer to said central processor unit for transmitting signals between said central processor unit and said microcomputer unit, and 10. error detection logic in said sequencer unit for detecting errors, including sector fault errors, address header errors and read data errors, in said data processing system, 11. whereby said central processor unit can send write signals to said peripheral storage device through said sequencer unit and receive read signals from said peripheral storage device through said multiplexer means and said sequencer unit when said gating means is enabled and whereby test write signals can be sent from said central processor unit to said sequencer and then be returned to said central processor unit through said microcomputer unit and test read signals can be generated in said microcomputer unit and sent to said central processor unit through said multiplexer means and said sequencer unit when said peripheral storage device is disabled from said sequencer unit.
Claim 17
Dependent Claim
263 words
multiplexer means having an output connected to said sequencer unit, an input connected to said microprocessor and an input connected to the output of said peripheral storage device for transferring data to said sequencer unit from either said microcomputer unit or said peripheral storage device, 7. data transfer bus means connecting said sequencer unit to said microcomputer for enabling data signals sent to said sequencer unit to be transmitted to said microcomputer unit, 8. data transfer means connecting said central processor unit to said sequencer unit for enabling data signals to be sent between said central processor unit and said sequencer unit, 9. data transfer bus means connecting said microcomputer to said central processor unit for transmitting signals between said central processor unit and said microcomputer unit, and 10. error detection logic in said sequencer unit for detecting errors, including sector fault errors, address header errors and read data errors, in said data processing system, 11. whereby said central processor unit can send write signals to said peripheral storage device through said sequencer unit and receive read signals from said peripheral storage device through said multiplexer means and said sequencer unit when said gating means is enabled and whereby test write signals can be sent from said central processor unit to said sequencer and then be returned to said central processor unit through said microcomputer unit and test read signals can be generated in said microcomputer unit and sent to said central processor unit through said multiplexer means and said sequencer unit when said peripheral storage device is disabled from said sequencer unit.
Claim 18
Dependent Claim
20 words
The data processing system in accordance with claim 12 and wherein said peripheral storage device is a disk drive system.
Claim 19
Dependent Claim
18 words
The data processing system in accordance with claim 13 and wherein said gating means comprises an AND gate.
Claim 20
Dependent Claim
28 words
The data processing system in accordance with claim 12 and wherein said sequencer unit comprises a sequencer, data serialization and deserialization logic circuitry and error detection logic circuitry.
Claim 21
Dependent Claim
33 words
The data processing system in accordance with claim 12 and wherein said microcomputer unit comprises a microprocessor connected to logic circuitry of said unit for interfacing said unit to said central processor unit.
Claim 22
Dependent Claim
31 words
The data processing system in accordance with claim 12 and wherein said data transfer means connecting said sequencer to said central processor unit includes a buffer for temporary storage of data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-26 | 1985-10-26 | 1986-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-26 | 1989-10-26 | 1990-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-26 | 1993-10-26 | 1994-04-27 | $7700.00 | Window Closed / Lapsed |