Means for virtual deskewing of high/intermediate/low DUT data

Claim 1

An apparatus for accomplishing virtual data deskewing of a first data signal and at least one additional data signal, each said at least one additional data signal having an associated data skew which corresponds to a delay amount between when said first data signal becomes valid and when said respective at least one additional data signal becomes valid, said apparatus comprising: a receiver circuit connected to receive said first data signal and said at least one additional data signal, said receiver circuit comprising: a plurality of data mode detection mechanisms, at least one corresponding to each of said first data signal and said at least one additional data signal, and each selectable to operate in one or the other of a window compare mode or a transparent mode and which receives said corresponding one of said first data signal or said at least one additional data signal and generates a respective data mode signal corresponding to said respective first data signal or said at least one additional data signal; a plurality of data capture mechanisms, at least one corresponding to each of said first data signal and said at least one additional data signal, wherein each of said plurality of data capture mechanisms receives said respective data mode signal corresponding to said first data signal or said at least one additional data signal and a corresponding clock signal, and captures said respective data mode signal in synchronization with said corresponding clock signal to generate a deskewed data state signal that corresponds to respective data mode signal, said corresponding clock signal having an associated clock skew substantially equal to said delay amount of said associated data skew between said corresponding first data signal and said at least one additional data signal.

Claim 2

An apparatus for accomplishing virtual data deskewing of a first data signal and at least one additional data signal, each said at least one additional data signal having an associated data skew which corresponds to a delay amount between when said first data signal becomes valid and when said respective at least one additional data signal becomes valid, said apparatus comprising: a receiver circuit connected to receive said first data signal and said at least one additional data signal, said receiver circuit comprising: a plurality of data mode detection mechanisms, at least one corresponding to each of said first data signal and said at least one additional data signal, and each selectable to operate in one or the other of a window compare mode or a transparent mode and which receives said corresponding one of said first data signal or said at least one additional data signal and generates a respective data mode signal corresponding to said respective first data signal or said at least one additional data signal; a plurality of data capture mechanisms, at least one corresponding to each of said first data signal and said at least one additional data signal, wherein each of said plurality of data capture mechanisms receives said respective data mode signal corresponding to said first data signal or said at least one additional data signal and a corresponding clock signal, and captures said respective data mode signal in synchronization with said corresponding clock signal to generate a deskewed data state signal that corresponds to respective data mode signal, said corresponding clock signal having an associated clock skew substantially equal to said delay amount of said associated data skew between said corresponding first data signal and said at least one additional data signal.

Claim 7

An apparatus for accomplishing virtual data deskewing of a high-level data signal and a low-level data signal to generate an output signal representative of a data signal state of a data signal, said data signal state being in one of a high data state wherein said data signal is above a high voltage threshold, a low data state wherein said data signal is below a low voltage threshold, or an intermediate state wherein said data signal is above said low voltage threshold and below said high voltage threshold, said apparatus comprising: a receiver circuit connected to receive said high-level data signal and said low-level data signal, said receiver circuit comprising: a plurality of data mode detection mechanisms, at least one corresponding to each of said high-level data signal and said low-level data signal, and each selectable to operate in one or the other of a window compare mode or a transparent mode and which receives said corresponding one of said high-level data signal or said low-level data signal and generates a respective high data mode signal corresponding to said respective high-level data signal or a respective low data mode signal corresponding to said low-level data signal; a plurality of data capture mechanisms, at least one corresponding to each of said high-level data signal and said low-level data signal, wherein each of said plurality of data capture mechanisms either receives said respective high data mode signal and a corresponding delayed high clock signal and captures said respective high data mode signal in synchronization with said corresponding delayed high clock signal to generate a deskewed high data state signal, or receives said respective low data mode signal and a corresponding delayed low clock signal and captures said respective low data mode signal in synchronization with said corresponding delayed low clock signal to generate a deskewed low data state signal, said high delayed clock signal and said low delayed clock signal having an associated clock skew substantially equal to said delay amount of said associated data skew between said corresponding high-level data signal and said low-level data signal.

Claim 8

An apparatus for accomplishing virtual data deskewing of a high-level data signal and a low-level data signal to generate an output signal representative of a data signal state of a data signal, said data signal state being in one of a high data state wherein said data signal is above a high voltage threshold, a low data state wherein said data signal is below a low voltage threshold, or an intermediate state wherein said data signal is above said low voltage threshold and below said high voltage threshold, said apparatus comprising: a receiver circuit connected to receive said high-level data signal and said low-level data signal, said receiver circuit comprising: a plurality of data mode detection mechanisms, at least one corresponding to each of said high-level data signal and said low-level data signal, and each selectable to operate in one or the other of a window compare mode or a transparent mode and which receives said corresponding one of said high-level data signal or said low-level data signal and generates a respective high data mode signal corresponding to said respective high-level data signal or a respective low data mode signal corresponding to said low-level data signal; a plurality of data capture mechanisms, at least one corresponding to each of said high-level data signal and said low-level data signal, wherein each of said plurality of data capture mechanisms either receives said respective high data mode signal and a corresponding delayed high clock signal and captures said respective high data mode signal in synchronization with said corresponding delayed high clock signal to generate a deskewed high data state signal, or receives said respective low data mode signal and a corresponding delayed low clock signal and captures said respective low data mode signal in synchronization with said corresponding delayed low clock signal to generate a deskewed low data state signal, said high delayed clock signal and said low delayed clock signal having an associated clock skew substantially equal to said delay amount of said associated data skew between said corresponding high-level data signal and said low-level data signal.

Claim 18

A method for accomplishing virtual data deskewing of a high-level comparator signal and a low-level comparator signal which, if properly deskewed, together indicate a data signal state of a data signal, said data signal state being in one of a high data state wherein said data signal is above a high voltage threshold, a low data state wherein said data signal is below a low voltage threshold, or an intermediate state wherein said data signal is above said low voltage threshold and below said high voltage thresholds comprising the steps of: (a) generating a delayed high clock signal and a delayed low clock signal which differ in delay amount in an amount substantially equal to a data skew caused by different delays in respective data paths of said high-level comparator signal and said low-level comparator signal; (b) utilizing said delayed high clock signal to delay and capture one or more high-level window compare function outputs derived from said high-level comparator signal, and said delayed low clock signal to delay and capture one or more low-level window compare function outputs derived from said low-level comparator signal; and (c) decoding said high-level window compare function outputs and said low-level window compare function outputs to produce a high data signal indicating that said data signal is in said high data state and a low data signal indicating that said data signal is in said low data state.

Claim 19

A method for accomplishing virtual data deskewing of a high-level comparator signal and a low-level comparator signal which, if properly deskewed, together indicate a data signal state of a data signal, said data signal state being in one of a high data state wherein said data signal is above a high voltage threshold, a low data state wherein said data signal is below a low voltage threshold, or an intermediate state wherein said data signal is above said low voltage threshold and below said high voltage thresholds comprising the steps of: (a) generating a delayed high clock signal and a delayed low clock signal which differ in delay amount in an amount substantially equal to a data skew caused by different delays in respective data paths of said high-level comparator signal and said low-level comparator signal; (b) utilizing said delayed high clock signal to delay and capture one or more high-level window compare function outputs derived from said high-level comparator signal, and said delayed low clock signal to delay and capture one or more low-level window compare function outputs derived from said low-level comparator signal; and (c) decoding said high-level window compare function outputs and said low-level window compare function outputs to produce a high data signal indicating that said data signal is in said high data state and a low data signal indicating that said data signal is in said low data state.