Clock distribution apparatus with current sensed skew cancelling

Claim 2

A clock distribution circuit for achieving substantially simultaneous arrival of timing events at a plurality of digital subsystems comprising: a clocking means for generating said timing events, said clocking means having a plurality of outputs, each of said outputs being effective for supplying a copy of said timing events; a plurality of transmission lines; a plurality of current sensing means; a plurality of delay means; each of said plurality of digital subsystems being coupled to said clock distribution circuit at only a corresponding one of said plurality of outputs, each of said plurality of digital subsystems being coupled to said corresponding one of said outputs via a single one of said transmission lines whereby each of said digital subsystems receives one of said conies of said timing events; each of said plurality of current sensing means being coupled to a corresponding one of said plurality of transmission lines, each of said current sensing means being effective for determining a current flow time during which current flows in said corresponding one of said transmission lines; each of said plurality of transmission lines being coupled to a corresponding one of said plurality of delay means, each of said plurality of delay means being effective for delaying said timing events by an amount dependent on a predetermined maximum delay reduced by one-half said current flow time whereby the propagation delay of said timing events from each of said outputs to its corresponding one of said digital subsystems is equalized to said predetermined maximum delay.

Claim 3

The circuit of claim 1 further defined by phase adjusting means coupled to said clocking means for time shifting said timing events by a desired amount.

Claim 4

The circuit of claim 2 wherein said phase adjusting means is a phase-locked loop.

Claim 5

The circuit of claim 1 further defined by a frequency dividing means coupled between said clocking means and one of said plurality of delay means whereby the frequency of said timing events is altered.

Claim 6

The circuit of claim 1 wherein at least one of said plurality of delay means is coupled to a non-volatile memory storing a signal representing said predetermined maximum delay reduced by one-half its corresponding said current flow time.

Claim 7

A clock distribution circuit for achieving simultaneous arrival of clock timing events at digital subsystems comprising: a source of said clock timing events having a plurality of output points, each of said plurality of output points being connected to a distribution network, said distribution network consisting of a plurality of transmission lines having different lengths; each of said digital subsystems receiving said clock timing events via a variable delay element connected by means of one of said transmission lines, said transmission lines being terminated at said digital subsystems with an impedance at least partially reflective of said clock timing events, each of said digital subsystems being coupled to said clock distribution circuit at only one of said output points via one of said transmission lines; a plurality of current sensing means for sensing a flow of current in each of said transmission lines; a plurality of time measuring means for determining a current flow time during which current flows in each of said transmission lines as determined by said plurality of current sensing means, said current flow time being the propagation time of said clock timing events through each of said transmission lines from said clock distribution circuit to said digital subsystems and back; and an arithmetic unit means coupled to each time measuring means for determining one-half said current flow time and subtracting said one-half current flow time from a predetermined maximum time, the resultant value being a variable delay signal coupled to a corresponding one of said variable delay elements, each of said variable delay elements being coupled to one of said plurality of transmission lines and effective for delaying said clock timing events by an amount determined by said variable delay signal.

Claim 8

A clock distribution circuit for achieving simultaneous arrival of clock timing events at digital subsystems comprising: a source of said clock timing events having a plurality of output points, each of said plurality of output points being connected to a distribution network, said distribution network consisting of a plurality of transmission lines having different lengths; each of said digital subsystems receiving said clock timing events via a variable delay element connected by means of one of said transmission lines, said transmission lines being terminated at said digital subsystems with an impedance at least partially reflective of said clock timing events, each of said digital subsystems being coupled to said clock distribution circuit at only one of said output points via one of said transmission lines; a plurality of current sensing means for sensing a flow of current in each of said transmission lines; a plurality of time measuring means for determining a current flow time during which current flows in each of said transmission lines as determined by said plurality of current sensing means, said current flow time being the propagation time of said clock timing events through each of said transmission lines from said clock distribution circuit to said digital subsystems and back; and an arithmetic unit means coupled to each time measuring means for determining one-half said current flow time and subtracting said one-half current flow time from a predetermined maximum time, the resultant value being a variable delay signal coupled to a corresponding one of said variable delay elements, each of said variable delay elements being coupled to one of said plurality of transmission lines and effective for delaying said clock timing events by an amount determined by said variable delay signal.

Claim 9

The circuit of claim 6 further defined by phase adjusting means connected at said source of clock timing events for time shifting said clock timing events by a desired amount.

Claim 10

The circuit of claim 7 wherein said phase adjusting means is a phase-locked loop.

Claim 11

The circuit of claim 6 further defined by a frequency dividing means coupled between said source of clock timing events and said variable delay elements for the purpose of altering the frequency of said clock timing events.

Claim 12

The circuit of claim 6 wherein one of said variable delay elements receives said timing events at a frequency different from another of said variable delay elements.

Claim 13

The circuit of claim 6 further comprising a second plurality of variable delay elements responsive to said plurality of time measuring means and coupled to control inputs of said arithmetic unit, said plurality of second variable delay elements being further coupled to receive an additional input signal and effective for delaying said additional input signal to said arithmetic unit by an amount proportional to said current flow time.

Claim 14

The circuit of claim 6 wherein said plurality of variable delay elements are servo controlled.

Claim 15

The circuit of claim 6 wherein each of said transmission lines has a matched impedance input.

Claim 16

The circuit of claim 6 wherein said variable delay signal of said arithmetic unit is an analog voltage coupled to a non-volatile memory cell for storing said analog voltage.

Claim 17

The circuit of claim 6 wherein said arithmetic unit means is coupled to a non-volatile memory for storing said variable delay signal.

Claim 18

The circuit of claim 6 wherein each of said time measuring means for determining a current flow time during which current flows in a respective one of said plurality of transmission lines accepts the termination of current flow as being the point when a predetermined percentage of charge needed to change the logic state of said respective one of said plurality of said transmission lines has been accumulated on said respective transmission line.

Claim 19

A clock distribution circuit for supplying clock timing events to a digital subsystem and for achieving a clock delay time of said clock timing events substantially similar to a predetermined maximum delay, said clock distribution circuit comprising: a source of said clock timing events connected to a variable delay element, said variable delay element being coupled to an output lead; a transmission line for coupling said output lead to said digital subsystem; said digital subsystem receiving said clock timing events through said variable delay elements, output lead and said transmission line, said transmission line being terminated at said digital subsystem with an impedance at least partially reflective of said clock timing events and effective for producing a reflection signal along said transmission from said digital subsystem to said output lead; a current monitoring means coupled to monitor current through said output lead; a time measuring means coupled to said current monitoring means and effective for determining a measure of time substantially similar to one-half the time during which current flows through said output lead, this measure of time being similar to a forward propagation time during which a clock timing event propagates from said output lead to said digital subsystem; and a servo means responsive to said time measuring means and coupled to monitor a variable delay through said variable delay element, said servo means being effective for servo control of said variable delay element and for adjusting said variable delay element such that the sum of said variable delay through said variable delay element plus said forward propagation time substantially equals said maximum delay time.

Claim 20

A clock distribution circuit for supplying clock timing events to a digital subsystem and for achieving a clock delay time of said clock timing events substantially similar to a predetermined maximum delay, said clock distribution circuit comprising: a source of said clock timing events connected to a variable delay element, said variable delay element being coupled to an output lead; a transmission line for coupling said output lead to said digital subsystem; said digital subsystem receiving said clock timing events through said variable delay elements, output lead and said transmission line, said transmission line being terminated at said digital subsystem with an impedance at least partially reflective of said clock timing events and effective for producing a reflection signal along said transmission from said digital subsystem to said output lead; a current monitoring means coupled to monitor current through said output lead; a time measuring means coupled to said current monitoring means and effective for determining a measure of time substantially similar to one-half the time during which current flows through said output lead, this measure of time being similar to a forward propagation time during which a clock timing event propagates from said output lead to said digital subsystem; and a servo means responsive to said time measuring means and coupled to monitor a variable delay through said variable delay element, said servo means being effective for servo control of said variable delay element and for adjusting said variable delay element such that the sum of said variable delay through said variable delay element plus said forward propagation time substantially equals said maximum delay time.

Claim 21

The circuit of claim 17 wherein said servo means includes a capacitor having a charging circuit means for receiving charge proportional to a time equal to said maximum delay time and further having a first and a second discharging circuit means, said first discharging circuit means being effective for discharging said capacitor for a first discharging time comparable to said measured forward propagation time, said second discharging circuit means being effective for discharging said capacitor for a second discharging time estimated to be the difference between said maximum delay time and said measured forward propagation time, the voltage across said capacitor being a control input to said variable delay element.

Claim 22

The circuit of claim 18 wherein said first discharging circuit means further includes a current source receiving input signals from said time measuring means and from said variable delay element.

Claim 23

The circuit of claim 18 wherein said second discharging circuit means further includes a current source receiving input signals from said source of clock timing events and from one of said variable delay element.

Claim 24

The circuit of claim 17 wherein said time measuring means is coupled to a non-volatile memory for storing said forward propagation time.

Claim 25

The circuit of claim 18 wherein said servo means is coupled to a non-volatile memory for storing said voltage across said capacitor.

Claim 26

The circuit of claim 18 wherein said charging circuit means further including a current source receiving input control signals from a means for measuring said maximum delay time.