Skew-free clock signal distribution network in a microprocessor of a computer system

Claim 2

A computer system, comprising: (A) a system bus; (B) a plurality of peripheral devices, each of which being coupled to the system bus; (C) a memory coupled to the system bus; (B) a central processing unit (CPU) coupled to the system bus, wherein the CPU further comprises (i) a plurality of units, each performing a predetermined function for the CPU; (ii) a clock signal distribution network for distributing a global clock signal to the plurality of units, wherein the clock signal distribution network further comprises (1) clock generation circuitry coupled to receive a clock input signal for generating the global clock signal; (2) clock driving circuitry coupled to receive the global clock signal from the clock generation circuitry for driving the global clock signal to the plurality of units; (3) electrical connection circuitry having a plurality of connection lines coupled to receive the global clock signal from the clock driving circuitry for coupling the global clock signal to the plurality of units, wherein each of the plurality of connection lines generates a signal transfer delay to the global clock signal; (4) length equalizing circuitry coupled between the clock driving circuitry and the electrical connection circuitry for equalizing the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time; and (5) area buffer circuitry in each of the plurality of units coupled to one of the plurality of connection lines for standardizing an input load of each of the plurality of units to the clock driving circuitry, wherein the area buffer circuitry receives the global signal from one of the plurality of connection lines and couples the global clock signal to its respective unit.

Claim 3

The computer system of claim 1, wherein the length equalizing circuitry comprises a plurality of serpentine lines, each being coupled to one of the plurality of connection lines, wherein the plurality of serpentine lines are of different lengths such that the global clock signal can reach the area buffer circuitry of each of the plurality of units via each of the plurality serpentine lines and each of the plurality of connection lines at the same time.

Claim 4

The computer system of claim 2, wherein some of the plurality of serpentine lines has at least one S-shaped curve, wherein the S-shaped curve has two spacings, each being approximately 3.5 micron wide.

Claim 5

The computer system of claim 3, wherein the length equalizing circuitry further comprises a ground-coupled line located in each of the spacings of the S-shaped curve for avoiding short circuiting caused by skinning effect of the S-shaped curve.

Claim 6

The computer system of claim 4, wherein the area buffer circuitry comprises two inverters, wherein each of the inverters are large enough to isolate the load of its respective unit to the clock driving means.

Claim 7

The computer system of claim 5, wherein each of the inverters is a BICMOS inverter.

Claim 8

A computer system, comprising: (A) a system bus; (B) a plurality of peripheral devices, each of which being coupled to the system bus; (C) a memory coupled to the system bus; (B) a central processing unit (CPU) coupled to the system bus, wherein the CPU further comprises (i) a plurality of units, each performing a predetermined function for the CPU; (ii) a clock signal distribution network for distributing a global clock signal to the plurality of units, wherein the clock signal distribution network further comprises (1) clock generation means coupled to receive a clock input signal for generating a first clock signal, wherein the clock generation means generates an input delay to the first clock signal; (2) phase locked loop means coupled to the clock generation means for generating a controllable delay to the first clock signal to become the global clock signal; (3) clock driving means coupled to receive the global clock signal from the phase locked loop means for driving the global clock signal to the plurality of units; (4) electrical connection means having a plurality of connection lines coupled to receive the global clock signal from the clock driving means for coupling the global clock signal to the plurality of units, wherein each of the plurality of connection lines generates a signal transfer delay to the global clock signal, wherein the plurality of connection lines include a dummy connection line; (5) length equalizing means coupled between the clock driving means and the electrical connection means for equalizing the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time; (6) area buffer means in each of the plurality of units coupled to one of the plurality of connection lines for standardizing an input load of each of the plurality of units to the clock driving means, wherein the area buffer means receives the global signal from one of the plurality of connection lines and couples the global clock signal to its respective unit; and (7) dummy buffer means coupled to the dummy connection line for generating the input delay to the global clock signal, wherein the dummy buffer means has a dummy input delay approximately equal to the input delay of the clock generation means, wherein the dummy buffer means applies its output signal to the phase locked loop means, wherein the phase locked loop means controls the generation of the controllable delay to the first clock signal in response to the output signal from the dummy buffer means such that the global signal received at each of the plurality of units is synchronized to the clock input signal independent of a process variation, a temperature variation, and a voltage supply variation.

Claim 9

A computer system, comprising: (A) a system bus; (B) a plurality of peripheral devices, each of which being coupled to the system bus; (C) a memory coupled to the system bus; (B) a central processing unit (CPU) coupled to the system bus, wherein the CPU further comprises (i) a plurality of units, each performing a predetermined function for the CPU; (ii) a clock signal distribution network for distributing a global clock signal to the plurality of units, wherein the clock signal distribution network further comprises (1) clock generation means coupled to receive a clock input signal for generating a first clock signal, wherein the clock generation means generates an input delay to the first clock signal; (2) phase locked loop means coupled to the clock generation means for generating a controllable delay to the first clock signal to become the global clock signal; (3) clock driving means coupled to receive the global clock signal from the phase locked loop means for driving the global clock signal to the plurality of units; (4) electrical connection means having a plurality of connection lines coupled to receive the global clock signal from the clock driving means for coupling the global clock signal to the plurality of units, wherein each of the plurality of connection lines generates a signal transfer delay to the global clock signal, wherein the plurality of connection lines include a dummy connection line; (5) length equalizing means coupled between the clock driving means and the electrical connection means for equalizing the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time; (6) area buffer means in each of the plurality of units coupled to one of the plurality of connection lines for standardizing an input load of each of the plurality of units to the clock driving means, wherein the area buffer means receives the global signal from one of the plurality of connection lines and couples the global clock signal to its respective unit; and (7) dummy buffer means coupled to the dummy connection line for generating the input delay to the global clock signal, wherein the dummy buffer means has a dummy input delay approximately equal to the input delay of the clock generation means, wherein the dummy buffer means applies its output signal to the phase locked loop means, wherein the phase locked loop means controls the generation of the controllable delay to the first clock signal in response to the output signal from the dummy buffer means such that the global signal received at each of the plurality of units is synchronized to the clock input signal independent of a process variation, a temperature variation, and a voltage supply variation.

Claim 10

The computer system of claim 7, wherein the length equalizing means comprises a plurality of serpentine lines, each being coupled to one of the plurality of connection lines, wherein the plurality of serpentine lines are of different lengths such that the global clock signal can reach the area buffer means of each of the plurality of units via each of the plurality serpentine lines and each of the plurality of connection lines at the same time.

Claim 11

The computer system of claim 8, wherein each of the plurality of serpentine lines has at least one S-shaped curve, wherein the S-shaped curve has two spacings, each being approximately 3.5 micron wide.

Claim 12

The computer system of claim 9, wherein the length equalizing means further comprises a ground-coupled line located in each of the spacings of the S-shapecurve for avoiding short circuiting caused by a skinning effect in the S-shaped curve.

Claim 13

The computer system of claim 7, wherein the area buffer means comprises two inverters, wherein each of the inverters are large enough to isolate the load of its respective unit to the clock driving means.

Claim 14

The computer system of claim 11, wherein each of the inverters is a BICMOS inverter.