US4805095A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and a method for the selection of original data from a register log containing original and modified data
Assignee: NCR Voyix Corp
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Filing: 1985-12-23
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Granted: 1989-02-14
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Expires: 2005-12-23
Abstract
Abstract A circuit for maintaining copies of original index registers and copies of modified index registers such that in the event original copies of the index registers are needed, they may be restored. The circuit is for use in a fault tolerant system wherein in the event of a rollback, original copies of the index registers may be restored to a processor, even if some of the index registers were modified in the previous execution of a command by the processor.
Inventors
- 👤 Rolf D. Armstrong
- 👤 Jon M. Corcoran
- 👤 Victor F. Cole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
284 words
A circuit comprising: a multi-stage instruction pipeline having an execute stage of a current instruction partially overlap an interpret stage of the next instruction; a plurality of modifiable data registers connected and responsive to said pipeline, each of said data registers being modifiable such that its contents can be restored to an original state; a plurality of memory locations, each of said memory locations corresponding to a modifiable data register and having two data storage means, a first data storage means for storing the contents of each corresponding data register of each respective memory location in the original state thereof, and a second data storage means for storing the contents of corresponding data register of each respective memory location in a modified state thereof; a plurality of modified bit register means, one corresponding to each of said memory locations, each of said modified bit register means including means for selectively enabling a modified bit when the contents of the data register of its corresponding memory location in the modified state thereof is stored in one of its corresponding data storage means; and a plurality of valid bit register means, each having an input connected to a corresponding one of said modified bit register means, an output connected to its corresponding memory location, means for containing a valid bit whose condition is indicative of which one of the two data storage means of said corresponding memory location contains the original contents of the corresponding data register, and means for toggling the condition of said valid bit responsive to the enabling of the modified bit of said corresponding modified bit register means during the interpret stage and the execution stage of each multi-stage pipeline system instruction.
Claim 2
Dependent Claim
284 words
A circuit comprising: a multi-stage instruction pipeline having an execute stage of a current instruction partially overlap an interpret stage of the next instruction; a plurality of modifiable data registers connected and responsive to said pipeline, each of said data registers being modifiable such that its contents can be restored to an original state; a plurality of memory locations, each of said memory locations corresponding to a modifiable data register and having two data storage means, a first data storage means for storing the contents of each corresponding data register of each respective memory location in the original state thereof, and a second data storage means for storing the contents of corresponding data register of each respective memory location in a modified state thereof; a plurality of modified bit register means, one corresponding to each of said memory locations, each of said modified bit register means including means for selectively enabling a modified bit when the contents of the data register of its corresponding memory location in the modified state thereof is stored in one of its corresponding data storage means; and a plurality of valid bit register means, each having an input connected to a corresponding one of said modified bit register means, an output connected to its corresponding memory location, means for containing a valid bit whose condition is indicative of which one of the two data storage means of said corresponding memory location contains the original contents of the corresponding data register, and means for toggling the condition of said valid bit responsive to the enabling of the modified bit of said corresponding modified bit register means during the interpret stage and the execution stage of each multi-stage pipeline system instruction.
Claim 3
Dependent Claim
94 words
The circuit of claim 1 wherein each of said modified bit register means includes input means for receiving a control signal for causing previously selected modified bit register means to toggle the condition of its corresponding valid bit register means, thereby causing the condition of the valid bit of said corresponding valid bit register means to toggle such that the indication of which one of the two data storage means of said corresponding memory locations contains the original contents of the corresponding data register is changed from one data storage means to the other.
Claim 4
Dependent Claim
52 words
The circuit of claim 2 further comprising: input/output means connected to each of said valid bit register means for writing data into and for reading data out of each of said plurality of memory locations responsive to the condition of each respective valid bit of each of said valid bit register means.
Claim 5
Dependent Claim
60 words
The circuit of claim 3 wherein said input/output means includes decode means for decoding the condition of the respective valid bit of the respective valid bit register means corresponding to a memory location, such that said input/output means writes data to and reads data from the indicated one of said corresponding data storage means responsive to said respective valid bit.
Claim 6
Dependent Claim
49 words
The circuit of claim 4 wherein said input/output means includes a counter for sequentially counting the count of said memory locations from which data is to be read, and access means connected to said counter for accessing each of said memory locations responsive to the count of said counter.
Claim 7
Dependent Claim
76 words
The circuit of claim 5 wherein said input/output means further includes: addressable means for receiving an address of one of said memory locations into which data is to be written; and multiplexer means having a first input connected to said counter, a second input connected to said addressable means, and an output connected to said access means; said multiplexer means for multiplexing one of said count and said address for accessing one of said memory locations.
Claim 8
Dependent Claim
51 words
The circuit of claim 6 wherein said multiplexer means includes a control terminal for receiving a control signal having a first condition when data is to be written into one of said memory locations, and having a second condition when data is to be read from one of said memory locations.
Claim 9
Dependent Claim
27 words
The circuit of claim 7 wherein said input/output means further includes: transmission means for transmitting data between said plurality of memory locations and the modifiable data registers.
Claim 10
Dependent Claim
61 words
The circuit of claim 8 further comprising a second decode means connected to the output of said multiplexer means, said second decode means for decoding the output of said multiplexer means and for accessing said plurality of valid bit register means responsive thereto for determining the condition of the valid bit corresponding to the memory location accessed by said accessing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |