Method and apparatus for deskewing digital data

Claim 2

A receiver circuit for deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the receiver circuit comprising: a receiver clock circuit for generating a read clock signal; N data ports for receiving said N parallel digital data signals, where N is a positive integer greater than one; N tapped delay lines, each tapped delay line comprising a chain of delay elements through which said received digital data signal is transmitted, said chain of delay elements generating delayed digital signals at signal taps located after each of said delay elements; comparison means for comparing each said delayed digital signal from each said tapped delay line with an immediately neighboring delayed digital signal from the same tapped delay line so as to detect a signal transition indicative of said start bit; latch means, coupled to said receiver clock circuit and said tapped delay lines, for storing data corresponding to the signal tap at which said signal transition was located in each said tapped delay line at a predefined time during a cycle of said read clock signal; a multiplexer, coupled to said comparison means and said tapped delay lines, that outputs one of said delayed digital signals from each of said tapped delay lines in accordance with said data stored by said latch means; and logic means for storing new data in said latch means as each new burst of digital data signals is received; whereby said data signals output by the multiplexers are synchronized with said read clock signal and with each other.

Claim 3

A receiver circuit for deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the receiver circuit comprising: a receiver clock circuit for generating a latch clock signal and a read clock signal that is synchronized with said latch clock signal; N deskewing buffers, each buffer receiving a distinct one of said N parallel digital data signals, where N is a positive integer greater than one; each deskewing buffer comprising: a data port for receiving one of said digital data signals; a chain of J delay elements through which said digital data signal received by said data port is transmitted, said chain of J delay elements generating J delayed digital signals Data(i), for i=1 to J, at signal taps located after each of said delay elements; a latch that latches said J delayed digital signals Data(i) at a predefined time during each cycle of said latch clock signal, thereby generating J latched digital signals LData(i); a logic circuit coupled to said latch for comparing said latched digital signals LData(i) with the latched digital signals LData(i+1) for i=1 to J-1, generating J-1 comparison signals C(i); wherein when said predefined start bit is received and latched into said latch, one of comparison signals will have a predefined value distinct from all the other ones of said comparison signals; and a multiplexer which receives said data signals Data(i) and outputs one of said data signals Data(i) in accordance with the one of said comparison signals having said predefined value; and a latch clock inhibiting circuit for inhibiting generation of said latch clock signal after said predefined start bit has been received by all of said deskewing buffers; whereby said data signals output by the multiplexers in said deskewing buffers are synchronized with said read clock signal and with each other.

Claim 4

A receiver circuit for deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the receiver circuit comprising: a receiver clock circuit for generating a latch clock signal and a read clock signal that is synchronized with said latch clock signal; N deskewing buffers, each buffer receiving a distinct one of said N parallel digital data signals, where N is a positive integer greater than one; each deskewing buffer comprising: a data port for receiving one of said digital data signals; a chain of J delay elements through which said digital data signal received by said data port is transmitted, said chain of J delay elements generating J delayed digital signals Data(i), for i=1 to J, at signal taps located after each of said delay elements; a latch that latches said J delayed digital signals Data(i) at a predefined time during each cycle of said latch clock signal, thereby generating J latched digital signals LData(i); a logic circuit coupled to said latch for comparing said latched digital signals LData(i) with the latched digital signals LData(i+1) for i=1 to J-1, generating J-1 comparison signals C(i); wherein when said predefined start bit is received and latched into said latch, one of comparison signals will have a predefined value distinct from all the other ones of said comparison signals; and a multiplexer which receives said data signals Data(i) and outputs one of said data signals Data(i) in accordance with the one of said comparison signals having said predefined value; and a latch clock inhibiting circuit for inhibiting generation of said latch clock signal after said predefined start bit has been received by all of said deskewing buffers; whereby said data signals output by the multiplexers in said deskewing buffers are synchronized with said read clock signal and with each other.