Digital phase adjustment

Claim 2

Apparatus for adjusting, in relation to a local clock signal, the relative phase of a data signal arriving at data utilization circuitry, said apparatus comprising: means for introducing an adjustable relative delay between the arriving data signal and the local clock signal; means for obtaining binary samples of the arriving data signal for a variety of delay values; means for detecting discrepancies between the binary values of the samples for successive greater delay values and for generating a corresponding error signal which identifies the delay value associated with the occurrence of a discrepancy; and control means responsive to said error signal for applying a relative delay which is substantially different from said delay value which is associated with the occurrence of a discrepancy.

Claim 3

Apparatus as set forth in claim 1 further comprising means for averaging said error signal over multiple transitions in said data signal.

Claim 4

Apparatus as set forth in claim 1 wherein said means for introducing an adjustable relative delay comprise a plurality of delay lines providing progressively greater delays.

Claim 5

Apparatus for adjusting the phase of data signals arriving at data utilization circuitry, said apparatus comprising: a succession of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said lines thereby to obtain respective delayed data signals; selector means for providing one of sid delayed data signals to the utilization circuitry; means for detecting discrepancies between the delayed data signals obtained from adjacent delay lines in the succession; means for controlling said selector means to apply to the utilization circuitry a delayed data signal which is spaced a substantial distance along the succession from those adjacent delayed data signals which exhibit discrepancies.

Claim 6

Apparatus for adjusting the phase of data signals arriving at data utilization circuitry, said apparatus comprising: a succession of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said lines thereby to obtain respective delayed data signals; selector means for providing one of sid delayed data signals to the utilization circuitry; means for detecting discrepancies between the delayed data signals obtained from adjacent delay lines in the succession; means for controlling said selector means to apply to the utilization circuitry a delayed data signal which is spaced a substantial distance along the succession from those adjacent delayed data signals which exhibit discrepancies.

Claim 7

Apparatus for adjusting the phase of a data signal arriving at data utilization circuitry to adjust for uncontrollable phase shifts in the data signal originating apart from the data utilization circuitry, said apparatus comprising: a succession of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said delay lines thereby to obtain respective delayed data signals; selector means for providing, to said utilization circuitry, a selected one of the delayed data signals; means for comparing the delayed signals over a period of time and for setting said selector to a delayed data signal which is distant from the delayed data signals which bracket the most disparities.

Claim 8

Apparatus for adjusting the phase of a data signal arriving at data utilization circuitry to adjust for uncontrollable phase shifts in the data signal originating apart from the data utilization circuitry, said apparatus comprising: a succession of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said delay lines thereby to obtain respective delayed data signals; selector means for providing, to said utilization circuitry, a selected one of the delayed data signals; means for comparing the delayed signals over a period of time and for setting said selector to a delayed data signal which is distant from the delayed data signals which bracket the most disparities.

Claim 9

Apparatus for adjusting the phase of data signals arriving at data utilization circuitry to adjust for uncontrollable phase shifts in the data signal originating apart from the data utilization circuitry, said apparatus comprising: a plurality of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said lines thereby to obtain respective delayed data signals; selector means, responsive to a selection value signal, for providing to said utilization circuitry one of said delayed data signals selected in accordance with said selection value; respective latch means for acquiring and holding the instantaneous value of each said delayed data signal in response to a local clock signal; respective gate means responsive to the latched values for generating a signal indicating whether a transition occurred between the respective delays provided by successively adjacent delay lines, the outputs of said gate means collectively representing a possible choice of delays; means for comparing the gate generated signals over a period of time and for setting said selector to a delayed data signal which is distant from the delayed data signals which bracket the most transitions.

Claim 10

Apparatus for adjusting the phase of data signals arriving at data utilization circuitry to adjust for uncontrollable phase shifts in the data signal originating apart from the data utilization circuitry, said apparatus comprising: a plurality of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said lines thereby to obtain respective delayed data signals; selector means, responsive to a selection value signal, for providing to said utilization circuitry one of said delayed data signals selected in accordance with said selection value; respective latch means for acquiring and holding the instantaneous value of each said delayed data signal in response to a local clock signal; respective gate means responsive to the latched values for generating a signal indicating whether a transition occurred between the respective delays provided by successively adjacent delay lines, the outputs of said gate means collectively representing a possible choice of delays; means for comparing the gate generated signals over a period of time and for setting said selector to a delayed data signal which is distant from the delayed data signals which bracket the most transitions.

Claim 11

Apparatus for adjusting the phase of data signals arriving at data utilization circuitry to adjust for uncontrollable phase shifts in the data signal originating apart from the data utilization circuitry, said apparatus comprising: a plurality of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said lines thereby to obtain respective delayed data signals; selector means, responsive to a selection value signal, for providing to said utilization circuitry one of said delayed data signals selected in accordance with said selection value signal; respective latch means for acquiring and holding the instantaneous value of each said delayed data signal in response to a local clock signal; combinatorial logic means for combining the held data signals values to obtain signal representing degree of match; state machine logic for generating and varying said selection signals as a function of said degree of match signal in a sense tending to select the delayed data signal furthest from disparities in adjacent data signals.

Claim 12

Apparatus for adjusting the phase of data signals arriving at data utilization circuitry to adjust for uncontrollable phase shifts in the data signal originating apart from the data utilization circuitry, said apparatus comprising: a plurality of delay lines providing progressively greater delays; means for providing the arriving data signal to each of said lines thereby to obtain respective delayed data signals; selector means, responsive to a selection value signal, for providing to said utilization circuitry one of said delayed data signals selected in accordance with said selection value signal; respective latch means for acquiring and holding the instantaneous value of each said delayed data signal in response to a local clock signal; combinatorial logic means for combining the held data signals values to obtain signal representing degree of match; state machine logic for generating and varying said selection signals as a function of said degree of match signal in a sense tending to select the delayed data signal furthest from disparities in adjacent data signals.