US5430737A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for testing function of integrated circuit
Assignee: Renesas Electronics Corp
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Filing: 1993-12-22
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Granted: 1995-07-04
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Expires: 2013-12-22
Abstract
Abstract An apparatus for testing the function of an IC that has a discrimination circuit for discriminating the result of a function test regardless of a change in the output timing of output data from an IC being tested. The discrimination circuit makes a nondefective determination if a discrimination time range from a starting point, a time from the transmission by a first timing generating circuit, to an end point, a time from a transmission by a second timing/generating circuit, includes a time region in which the output data from the IC and predicted data of an IC tester coincide with each other. A function test applying a high power supply voltage Vcc to the IC and a function test applying a low voltage Vcc can respectively be correctly performed to determine whether the subject IC is nondefective while eliminating the necessity of changing the timing data of the first and second timing generating circuits.
Inventors
- 👤 Eisaku Yamashita
- 👤 Ryuuji Omura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937; G01R31/31935
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
508 words
An apparatus for testing the function of an integrated circuit (IC) comprising: a test pin for electrically contacting an IC to be tested; and a discrimination circuit for testing the function of the IC, said discrimination circuit comprising: a first timing-signal generator for supplying a discrimination start timing signal as a start point of a discrimination time range; a second timing-signal generator for supplying a discrimination completion timing signal as an end point of the discrimination time range; a test pattern transmitter for storing and transmitting test pattern data in response to the discrimination start timing signal supplied from said first time-signal generator; voltage comparison and discrimination means for comparing the output voltage from the IC to be tested with a predicted voltage data set in accordance with each of the test pattern data in the discrimination time range, and transmitting a nondefective discrimination signal indicating that the IC is not defective when the output voltage and the predicted voltage coincide in the discrimination time range, said voltage comparison and discrimination means including a high level comparative voltage generating circuit for generating high-level voltages, a low level comparative voltage generating circuit for generating low-level voltages, the predicted voltage data sets comprising the high-level and low-level voltages, respectively coupled to said high-level and low level comparative voltage generating circuits and said test pin, first and second comparator circuits for comparing the output voltages from the IC with the predicted voltage data set and for respectively outputting high-level comparative signals and low-level comparative signals in response, a first logic circuit for generating a logical product of (i) an output of said test pattern transmitter and the discrimination start timing signal and (ii) an output of said test pattern transmitter and the discrimination completion timing signal, and a second logic circuit for generating the nondefective signal in response to the outputs of said first logic circuit and of said first and second comparator circuits; a discrimination signal transmitter for transmitting a discrimination signal that starts at the start point and ends upon output of the nondefective discrimination signal transmitted from said voltage comparison and discrimination means in accordance with each of the test pattern data, said discrimination signal transmitter including a third logic circuit for generating respective logical products of the discrimination start timing signal and an output of said test pattern transmitter, and a fourth logic circuit for storing and gating the logical product from said third logic circuit and for transmitting the discrimination signal; and discrimination information transmitting means for transmitting a nondefective/defective signal indicating whether the IC is nondefective by latching the discrimination signal upon generation of the discrimination complete timing signal corresponding to the end point of the discrimination time range, a nondefective indication being given when the discrimination time range includes transmission of the nondefective discrimination signal, said discrimination information transmitting means including a fifth logic circuit for storing and gating the discrimination signal from said discrimination signal transmitter, and first and second latch circuits for latching the nondefective/defective signal output from the fifth logic circuit.
Claim 2
Independent Claim
508 words
An apparatus for testing the function of an integrated circuit (IC) comprising: a test pin for electrically contacting an IC to be tested; and a discrimination circuit for testing the function of the IC, said discrimination circuit comprising: a first timing-signal generator for supplying a discrimination start timing signal as a start point of a discrimination time range; a second timing-signal generator for supplying a discrimination completion timing signal as an end point of the discrimination time range; a test pattern transmitter for storing and transmitting test pattern data in response to the discrimination start timing signal supplied from said first time-signal generator; voltage comparison and discrimination means for comparing the output voltage from the IC to be tested with a predicted voltage data set in accordance with each of the test pattern data in the discrimination time range, and transmitting a nondefective discrimination signal indicating that the IC is not defective when the output voltage and the predicted voltage coincide in the discrimination time range, said voltage comparison and discrimination means including a high level comparative voltage generating circuit for generating high-level voltages, a low level comparative voltage generating circuit for generating low-level voltages, the predicted voltage data sets comprising the high-level and low-level voltages, respectively coupled to said high-level and low level comparative voltage generating circuits and said test pin, first and second comparator circuits for comparing the output voltages from the IC with the predicted voltage data set and for respectively outputting high-level comparative signals and low-level comparative signals in response, a first logic circuit for generating a logical product of (i) an output of said test pattern transmitter and the discrimination start timing signal and (ii) an output of said test pattern transmitter and the discrimination completion timing signal, and a second logic circuit for generating the nondefective signal in response to the outputs of said first logic circuit and of said first and second comparator circuits; a discrimination signal transmitter for transmitting a discrimination signal that starts at the start point and ends upon output of the nondefective discrimination signal transmitted from said voltage comparison and discrimination means in accordance with each of the test pattern data, said discrimination signal transmitter including a third logic circuit for generating respective logical products of the discrimination start timing signal and an output of said test pattern transmitter, and a fourth logic circuit for storing and gating the logical product from said third logic circuit and for transmitting the discrimination signal; and discrimination information transmitting means for transmitting a nondefective/defective signal indicating whether the IC is nondefective by latching the discrimination signal upon generation of the discrimination complete timing signal corresponding to the end point of the discrimination time range, a nondefective indication being given when the discrimination time range includes transmission of the nondefective discrimination signal, said discrimination information transmitting means including a fifth logic circuit for storing and gating the discrimination signal from said discrimination signal transmitter, and first and second latch circuits for latching the nondefective/defective signal output from the fifth logic circuit.
Claim 3
Dependent Claim
43 words
The apparatus of claim 1 wherein said first logic circuit includes a flip flop coupled to said first timing signal generator and said second timing signal generator and first and second AND gates coupled to said flip flop and said test pattern transmitter.
Claim 4
Dependent Claim
38 words
The apparatus of claim 2 wherein said second logic circuit includes third and fourth AND gates respectively coupled to receive outputs from said first and second AND gates and respectively coupled to said first and second comparator circuits.
Claim 5
Dependent Claim
33 words
The apparatus of claim 1 wherein said third logic circuit includes fifth and sixth AND gates respectively coupled to receive outputs from said first timing signal generator and from said test pattern transmitter.
Claim 6
Dependent Claim
35 words
The apparatus of claim 4 wherein said fourth logic circuit includes fifth and sixth flip flops respectively connected to receive outputs from said first and second AND gates and said third and fourth AND gates.
Claim 7
Dependent Claim
32 words
The apparatus of claim 5 wherein said fifth logic circuit includes third and fourth flip-flops respectively connected to receive outputs from said first and second flip-flops and said second timing signal generator.
References Cited (Backward Citations)
US4313200A
Cited
US4271515A
Cited
US4497056A
Cited
US4584683A
Cited
US4656632A
Cited
US4775977A
Cited
JPS63140967A
Cited
US4893072A
Cited
US4928278A
Cited
JPH0377079A
Cited
JPH03210480A
Cited
US5164665A
Cited
JPH0611544A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |