US4775977A
Expired / Lapsed
US
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Pattern generating apparatus
Assignee: Yokogawa Electric Corp
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Filing: 1986-11-17
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Granted: 1988-10-04
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Expires: 2006-11-17
Abstract
Abstract A pattern generating apparatus for testing IC device includes an input/output mode memory, a pattern memory storing a driver pattern and an expected pattern, a driver pattern generator for outputting the driver pattern in response to the outputs of the pattern memory and the input/output mode memory, and an expected pattern generator for generating the expected pattern. The driver pattern is applied to the IC device whose output pattern is compared with the expected pattern in a comparison/decision circuit to decide whether the IC device is to be satisfactory or not. The pattern memory is of two-bit structure so that the driver pattern and the expected pattern can be varied in respect to the waveform in dependence on combinations of the two bits.
Inventors
- 👤 Masayoshi Dehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:41
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/3193
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
198 words
A pattern generating apparatus, comprising an input/output memory for storing a binary input/output pattern, said input/output memory having an output, a pattern memory for storing two binary patterns, said pattern memory having two outputs, a driver pattern generating circuit supplied as inputs thereto with the two outputs of the pattern memory and the output of the input/output memory for producing at the output thereof a driver pattern to be supplied to an electronic circuit to be tested, an expected pattern generating circuit supplied as inputs thereto with the two outputs of the pattern memory and the output of the input/output memory for producing an expected pattern for use as a reference relative to the actual pattern returned from the electronic circuit to be tested, said driver pattern generating circuit being operated when the output of the input/output memory indicates an input-mode so as to generate said driver pattern based on a combination of the two binary patterns from the pattern memory, said expected pattern generating circuit being operated when the output of said input/output memory indicates an output-mode so as to generate said expected pattern based on the combination of the two binary patterns from the pattern emory.
Claim 2
Dependent Claim
198 words
A pattern generating apparatus, comprising an input/output memory for storing a binary input/output pattern, said input/output memory having an output, a pattern memory for storing two binary patterns, said pattern memory having two outputs, a driver pattern generating circuit supplied as inputs thereto with the two outputs of the pattern memory and the output of the input/output memory for producing at the output thereof a driver pattern to be supplied to an electronic circuit to be tested, an expected pattern generating circuit supplied as inputs thereto with the two outputs of the pattern memory and the output of the input/output memory for producing an expected pattern for use as a reference relative to the actual pattern returned from the electronic circuit to be tested, said driver pattern generating circuit being operated when the output of the input/output memory indicates an input-mode so as to generate said driver pattern based on a combination of the two binary patterns from the pattern memory, said expected pattern generating circuit being operated when the output of said input/output memory indicates an output-mode so as to generate said expected pattern based on the combination of the two binary patterns from the pattern emory.
Claim 3
Dependent Claim
62 words
A pattern generating apparatus according to claim 1, said apparatus being used for testing an electronic device, wherein said driver pattern is applied to said device under test, further including decision means for comparing the output pattern signal produced by said electronic device in response to said driver pattern with said expected pattern to decide whether said device is acceptable or not.
Claim 4
Dependent Claim
43 words
A pattern generating apparatus according to claim 2, further including means for generating an inhibit signal in dependence on a combination of the two outputs of said pattern memory and the output of said input/output memory to inhibit operation of said decision means.
Claim 5
Dependent Claim
39 words
A pattern generating apparatus according to claim 2, further including means for generating a Z-mode signal in dependence on a combination of said two outputs of said pattern memory to check said electronic device in a high-impedance state thereof.
Claim 6
Dependent Claim
118 words
A pattern generating apparatus for use in testing an electronic device by applying a driver pattern signal thereto, comprising: means for producing a coded signal comprising multiple bits in parallel, a driver pattern generating circuit for producing, when enabled, a driver pattern signal in response to a preselected value of said multiple bits, an expected pattern generating circuit for producing, when enabled, and expected pattern signal in response to a preselected value of said multiple bits, means for producing a signal for alternately enabling said driver pattern and expected pattern generating circuits, means for applying the driver pattern signal to said electronic device, and means for comparing the expected pattern signal with an output of the electronic device.
Claim 7
Dependent Claim
118 words
A pattern generating apparatus for use in testing an electronic device by applying a driver pattern signal thereto, comprising: means for producing a coded signal comprising multiple bits in parallel, a driver pattern generating circuit for producing, when enabled, a driver pattern signal in response to a preselected value of said multiple bits, an expected pattern generating circuit for producing, when enabled, and expected pattern signal in response to a preselected value of said multiple bits, means for producing a signal for alternately enabling said driver pattern and expected pattern generating circuits, means for applying the driver pattern signal to said electronic device, and means for comparing the expected pattern signal with an output of the electronic device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-04 | 1992-04-04 | 1992-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-04 | 1996-04-04 | 1996-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-04 | 2000-04-04 | 2000-10-04 | $7700.00 | Window Closed / Lapsed |