US5336944A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Detector circuit for detecting state changes of a binary signal
Assignee: Advantest Singapore Pte Ltd
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Filing: 1992-10-22
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Granted: 1994-08-09
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Expires: 2012-10-22
Abstract
Abstract A detector circuit, preferably for an integrated circuit tester, compares an unknown binary signal with two reference voltages. The outputs of comparators are fed to a 1-of-n decoder whose outputs are, in turn, fed to latch circuits. Those latch circuits comprise a feedback loop which is activated by a control signal such that they may be operated either in a transmission mode or in a mode wherein all states of the unknown binary signal A during a prescribed time window may be recorded. The outputs of latch circuits are fed to D flip-flops, in order to sample the outputs of the latch circuits.
Inventors
- 👤 Martin Fischer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:56
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16566; G01R19/1659; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31917; G01R31/31924
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
89 words
A detector circuit for detecting state changes of a level of a binary signal comprising: comparator circuit means for receiving said level of said binary signal and for providing an output indicative of a comparison of said level of said binary signal with a reference; a 1-of-n decoder coupled where n is an integer to said output of said comparator circuit means; and latch circuit means connected with at least one output of said 1-of-n decoder, said latch circuit means including a feedback loop activatable by a control signal.
Claim 2
Dependent Claim
89 words
A detector circuit for detecting state changes of a level of a binary signal comprising: comparator circuit means for receiving said level of said binary signal and for providing an output indicative of a comparison of said level of said binary signal with a reference; a 1-of-n decoder coupled where n is an integer to said output of said comparator circuit means; and latch circuit means connected with at least one output of said 1-of-n decoder, said latch circuit means including a feedback loop activatable by a control signal.
Claim 3
Dependent Claim
41 words
A detector circuit according to claim 1, wherein said feedback loop locks said latch circuit means if an output signal of said 1-of-n decoder is at or enters a certain logic state, during a time window defined by said control signal.
Claim 4
Dependent Claim
30 words
A detector circuit according to claim 2, wherein said latch circuit means transmits the output signal of said 1-of-n decoder if the feedback loop is deactivated by said control signal.
Claim 5
Dependent Claim
68 words
A detector circuit according to claim 3, wherein said latch circuit means comprises: a first gate, having a first input connected with said output of said 1-of-n decoder; and a second gate, having a first input for receiving said control signal, and a second input connected with an output of said first gate, said second gate having an output connected with a second input of said first gate.
Claim 6
Dependent Claim
23 words
A detector circuit according to claim 4, wherein said first gate is an OR gate, and said second gate is an AND gate.
Claim 7
Dependent Claim
22 words
A detector circuit according to claim 1, wherein said latch circuit means has an output connected to a sample and hold circuit.
Claim 8
Dependent Claim
16 words
A detector circuit according to claim 6, wherein said sample and hold circuit includes a flip-flop.
Claim 9
Dependent Claim
33 words
A detector circuit according to claim 1, wherein said comparator circuit means comprises two comparator circuits and said latch circuit means comprises three latch circuits, and said 1-of-n decoder is a 1-of-3 decoder.
Claim 10
Independent Claim
83 words
A method for detecting state changes of a level of a binary signal in an integrated circuit tester, comprising the steps of: feeding said level of said binary signal to one input of at least one comparator circuit; feeding an output signal of said comparator circuit to an input of a 1-of-n decoder; and feeding an output signal of said 1-of-n decoder where n is an integer to a latch circuit comprising a feedback loop which may be activated by a control signal.
Claim 11
Independent Claim
83 words
A method for detecting state changes of a level of a binary signal in an integrated circuit tester, comprising the steps of: feeding said level of said binary signal to one input of at least one comparator circuit; feeding an output signal of said comparator circuit to an input of a 1-of-n decoder; and feeding an output signal of said 1-of-n decoder where n is an integer to a latch circuit comprising a feedback loop which may be activated by a control signal.
Claim 12
Dependent Claim
28 words
A method according to claim 9, comprising the additional step of: feeding an output signal of said latch circuit to an input of a sample and hold circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |