US5953635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlayer dielectric with a composite dielectric stack
Assignee: Intel Corp
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Filing: 1996-12-19
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Granted: 1999-09-14
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Expires: 2016-12-19
Abstract
Abstract A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposited and planarized using chemical mechanical polishing (CMP). The undoped oxide layer is denser than the phosphorous doped oxide layer, so the undoped oxide layer can be polished more uniformly than the phosphorous doped oxide layer and can serve as a polish stop for a subsequent tungsten plug polish. Also, the denser undoped oxide layer serves as a more effective moisture barrier than the doped oxide layer. Overall fabrication process complexity can be reduced by performing both oxide depositions in a single operation with no intervening densification or CMP steps.
Inventors
- 👤 Ebrahim Andideh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:15
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
91 words
A method of forming an interlayer dielectric on a semiconductor device, said method comprising the steps of: depositing a first insulating layer comprising phosphorous on said semiconductor device; sputter etching said first insulating layer to increase the conformality of said first insulating layer by redistributing a substantial amount of the material of said first insulating layer; depositing a second insulating layer directly on said first insulating layer, said second insulating layer being denser than said first insulating layer; and increasing the planarity of said second insulating layer using chemical mechanical polishing.
Claim 2
Independent Claim
91 words
A method of forming an interlayer dielectric on a semiconductor device, said method comprising the steps of: depositing a first insulating layer comprising phosphorous on said semiconductor device; sputter etching said first insulating layer to increase the conformality of said first insulating layer by redistributing a substantial amount of the material of said first insulating layer; depositing a second insulating layer directly on said first insulating layer, said second insulating layer being denser than said first insulating layer; and increasing the planarity of said second insulating layer using chemical mechanical polishing.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said first insulating layer is undensified.
Claim 4
Dependent Claim
26 words
The method of claim 1 further comprising a step of depositing a layer of silicon nitride prior to the step of depositing said first insulating layer.
Claim 5
Independent Claim
106 words
A method of forming an interlayer dielectric between a layer of semiconductor devices and a layer of interconnects, said method comprising the steps of: depositing a first oxide layer comprising phosphorous using plasma enhanced chemical vapor deposition; sputter etching said first oxide layer to increase the conformality of said first oxide layer by redistributing a substantial amount of the material of said first oxide layer; depositing a second oxide layer directly on said first oxide layer using plasma enhanced chemical vapor deposition, said second oxide layer being denser than said first oxide layer; and increasing the planarity of said second oxide layer using chemical mechanical polishing.
Claim 6
Independent Claim
106 words
A method of forming an interlayer dielectric between a layer of semiconductor devices and a layer of interconnects, said method comprising the steps of: depositing a first oxide layer comprising phosphorous using plasma enhanced chemical vapor deposition; sputter etching said first oxide layer to increase the conformality of said first oxide layer by redistributing a substantial amount of the material of said first oxide layer; depositing a second oxide layer directly on said first oxide layer using plasma enhanced chemical vapor deposition, said second oxide layer being denser than said first oxide layer; and increasing the planarity of said second oxide layer using chemical mechanical polishing.
Claim 7
Dependent Claim
12 words
The method of claim 4 wherein said second oxide layer is undoped.
Claim 8
Dependent Claim
25 words
The method of claim 4 further comprising a step of densifying said first oxide layer prior to the step of depositing said second oxide layer.
Claim 9
Dependent Claim
44 words
The method of claim 4 wherein the thickness of said first oxide layer is less than 5,000 Angstroms and the thickness of said second oxide layer is greater than 5,000 Angstroms prior to the step of increasing the planarity of said second oxide layer.
Claim 10
Dependent Claim
49 words
The method of claim 4 further comprising the steps of: forming an opening in said first and second oxide layers; depositing a conductive material into said opening and onto said second oxide layer; and polishing said conductive material from said second oxide layer to form a conductive filled opening.
Claim 11
Independent Claim
157 words
A method of forming an interlayer dielectric between a layer of semiconductor devices and a layer of interconnects, said method comprising the steps of: depositing a phosphorous doped layer with a thickness of less than 5,000 A using plasma enhanced chemical vapor deposition; sputter etching said phosphorous doped oxide layer to increase the conformality of said phosphorous doped oxide layer by redistributing a substantial amount of the material of said phosphorous doped oxide layer; depositing an undoped oxide layer with a thickness of greater than 5,000 A using plasma enhanced chemical vapor deposition, said undoped oxide layer being denser than said phosphorous doped oxide layer; increasing the planarity of said undoped oxide layer using chemical mechanical polishing; forming an opening in said undoped and phosphorous doped oxide layers; depositing a conductive material into said opening and onto said undoped oxide layer; and polishing said conductive material from said undoped oxide layer to form a conductive filled opening.
Claim 12
Independent Claim
157 words
A method of forming an interlayer dielectric between a layer of semiconductor devices and a layer of interconnects, said method comprising the steps of: depositing a phosphorous doped layer with a thickness of less than 5,000 A using plasma enhanced chemical vapor deposition; sputter etching said phosphorous doped oxide layer to increase the conformality of said phosphorous doped oxide layer by redistributing a substantial amount of the material of said phosphorous doped oxide layer; depositing an undoped oxide layer with a thickness of greater than 5,000 A using plasma enhanced chemical vapor deposition, said undoped oxide layer being denser than said phosphorous doped oxide layer; increasing the planarity of said undoped oxide layer using chemical mechanical polishing; forming an opening in said undoped and phosphorous doped oxide layers; depositing a conductive material into said opening and onto said undoped oxide layer; and polishing said conductive material from said undoped oxide layer to form a conductive filled opening.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |