Multi-level interconnection CMOS devices with SOG

Abstract

Abstract PCT No. PCT/CA91/00343 Sec. 371 Date Apr. 30, 1993 Sec. 102(e) Date Apr. 30, 1993 PCT Filed Sep. 25, 1991 PCT Pub. No. WO92/06492 PCT Pub. Date Apr. 16, 1992.A method of manufacturing a semiconductor wafer, which includes performing a first metallization to deposit a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, depositing a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, etching via holes through the dielectric and spin-on glass layers to reach the tracks of the first interconnect layer, performing an in-situ desorption of physically and chemically bonded water vapour in a dry environment at a temperature of at least 400 DEG C. and not more than 550 DEG C. for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25 DEG C. the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks without re-exposure of the wafer to ambient conditions, and keeping this wafer under vacuum. This technique permits the reliable use of inorganic or quasi-inorganic spin-on glasses in non batch type sputtering equipment.

Inventors

• 👤 Luc Ouellet

Bibliographic Details