US5858876A
Expired / Lapsed
US
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Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1996-04-01
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Granted: 1999-01-12
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Expires: 2016-04-01
Abstract
Abstract A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
Inventors
- 👤 Peter Chew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:04
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
105 words
A method for forming a doped silicon oxide insulator layer upon a patterned substrate layer comprising: forming upon a semiconductor substrate a patterned substrate layer; forming upon the patterned substrate layer a doped silicon oxide insulator layer, the doped silicon oxide insulator layer being formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method, the Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employing a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
Claim 2
Independent Claim
105 words
A method for forming a doped silicon oxide insulator layer upon a patterned substrate layer comprising: forming upon a semiconductor substrate a patterned substrate layer; forming upon the patterned substrate layer a doped silicon oxide insulator layer, the doped silicon oxide insulator layer being formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method, the Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employing a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein the patterned substrate layer is a patterned insulator layer.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein the pattered substrate layer is a patterned conductor layer.
Claim 5
Dependent Claim
27 words
The method of claim 1 wherein a width of the apertures between the patterns of the patterned substrate layer is from about 3000 to about 6000 angstroms.
Claim 6
Dependent Claim
25 words
The method of claim 1 wherein an aspect ratio of the apertures between the patterns of the patterned substrate layer is at least about 1.0:1.
Claim 7
Dependent Claim
32 words
The method of claim 1 wherein the Tetra Ethyl Ortho Silicate (TEOS) silicon source material is supplied at a flow rate of about 400 to about 600 standard cubic centimeters per minute.
Claim 8
Dependent Claim
72 words
The method of claim 1 wherein the dopant source material is chosen from the group of dopant source materials consisting of borane (BH 3 ), diborane (B 2 H 6 ), phosphine (PH 3 ), Tri-Methyl Borate (TMB; B(OCH 3 ) 3 ), Tri-Ethyl Borate (TEB; B(OC 2 H 5 ) 3 ), Tri-Methyl Phosphite (TMP; P(OCH 3 ) 3 ) and Tri-Ethyl Phosphite (TEP; P(OC 2 H 5 ) 3 ).
Claim 9
Dependent Claim
28 words
The method of claim 1 wherein the dopant source material is supplied at a flow rate of about 10 to about 30 standard cubic centimeters per minute (sccm).
Claim 10
Dependent Claim
12 words
The method of claim 1 wherein the oxygen source material is oxygen.
Claim 11
Dependent Claim
29 words
The method of claim 1 wherein the oxygen source material is supplied at a flow rate of from about 500 to about 1000 standard cubic centimeters per minute (sccm).
Claim 12
Dependent Claim
35 words
The method of claim 1 wherein the etching gas is chosen from the group of etching gases consisting of C 1 -C 2 per-fluorocarbons, C 1 -C 2 hydro-fluorocarbons and nitrogen trifluoride (NF 3 ).
Claim 13
Dependent Claim
28 words
The method of claim 1 wherein the etching gas is supplied at a flow rate of from about 30 to about 120 standard cubic centimeters per minute (sccm).
Claim 14
Dependent Claim
52 words
The method of claim 1 wherein the Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etching method are simultaneously undertaken at a reactor chamber pressure of from about 5 to about 10 torr and a radio frequency power of from about 300 to about 700 watts.
Claim 15
Dependent Claim
23 words
The method of claim 1 wherein a thickness of the doped silicon oxide insulator layer is from about 5000 to about 8000 angstroms.
Claim 16
Independent Claim
127 words
A method for forming a doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit comprising: forming upon a semiconductor substrate an integrated circuit, the integrated circuit having at least one transistor formed therein; forming within the integrated circuit a patterned substrate layer; forming upon the patterned substrate layer a doped silicon oxide insulator layer, the doped silicon oxide insulator layer being formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method, the Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employing a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
Claim 17
Independent Claim
127 words
A method for forming a doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit comprising: forming upon a semiconductor substrate an integrated circuit, the integrated circuit having at least one transistor formed therein; forming within the integrated circuit a patterned substrate layer; forming upon the patterned substrate layer a doped silicon oxide insulator layer, the doped silicon oxide insulator layer being formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method, the Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employing a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
Claim 18
Dependent Claim
14 words
The method of claim 15 wherein the transistor is a Field Effect Transistor (FET).
Claim 19
Dependent Claim
28 words
The method of claim 15 wherein the patterned substrate layer is chosen from the group of patterned substrate layers consisting of patterned conductor layers and patterned insulator layers.
Claim 20
Dependent Claim
47 words
The method of claim 15 wherein: a width of the apertures between the patterns of the patterned substrate layer is from about 3000 to about 6000 angstroms; and, an aspect ratio of the apertures between the patterns of the patterned substrate layer is at least about 1.0:1.
Claim 21
Dependent Claim
32 words
The method of claim 15 wherein the Tetra Ethyl Ortho Silicate (TEOS) silicon source material is supplied at a flow rate of about 400 to about 600 standard cubic centimeters per minute.
Claim 22
Dependent Claim
95 words
The method of claim 15 wherein: the dopant source material is chosen from the group of dopant source materials consisting of borane (BH 3 ), diborane (B 2 H 6 ), phosphine (PH 3 ); Tri-Methyl Borate (TMB; B(OCH 3 ) 3 ), Tri-Ethyl Borate (TEB; B(OC 2 H 5 ) 3 ), Tri-Methyl Phosphite (TMP; P(OCH 3 ) 3 ) and Tri-Ethyl Phosphite (TEP; P(OC 2 H 5 ) 3 ); and, the dopant source material is supplied at a flow rate of about 10 to about 30 standard cubic centimeters per minute (sccm).
Claim 23
Dependent Claim
36 words
The method of claim 15 wherein: the oxygen source material is oxygen; and, the oxygen source material is supplied at a flow rate of from about 500 to about 1000 standard cubic centimeters per minute (sccm).
Claim 24
Dependent Claim
58 words
The method of claim 15 wherein: the etching gas is chosen from the group of etching gases consisting of C 1 -C 2 per-fluorocarbons, C 1 -C 2 hydro-fluorocarbons and nitrogen trifluoride (NF 3 ); and, the etching gas is supplied at a flow rate of from about 30 to about 120 standard cubic centimeters per minute (sccm).
Claim 25
Dependent Claim
52 words
The method of claim 15 wherein the Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method are simultaneously undertaken at a reactor chamber pressure of from about 5 to about 10 torr and a radio frequency power of from about 300 to about 700 watts.
Claim 26
Dependent Claim
22 words
The method of claim 15 wherein a thickness of the silicon oxide insulator layer is from about 5000 to about 8000 angstroms.
References Cited (Backward Citations)
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