US5510652A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polishstop planarization structure
Assignee: International Business Machines Corp
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Filing: 1994-10-06
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Granted: 1996-04-23
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Expires: 2014-10-06
Abstract
Abstract The invention provides a method for producing a substantially planar surface overlying features of a semiconductor structure. The method comprises forming alternating layers of a hard polishing material and a soft polishing material over the features of the semiconductor structure, and then polishing the alternating layers to form a substantially planar surface over the features. The method takes advantage of the polish rates of the various materials used as alternating layers to enhance the planarization process.
Inventors
- 👤 Peter A. Burke
- 👤 Michael A. Leach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:03
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
166 words
A semiconductor device having a substantially planar top surface thereof, said device comprising: a substrate having a top surface thereof; raised features positioned on said top surface of said substrate; one or more filled vias extending upward from said raised features, each of said filled vias having a top surface thereof; a first layer of a soft polishing material overlying said top surface of said substrate and surrounding said one or more filled vias; a second layer of a hard polishing material overlying said first layer of a soft polishing material; a third layer of a soft polishing material overlying said second layer of a hard polishing material; and a conformal fourth layer of a hard polishing material overlying said third layer of a soft polishing material, wherein portions of said fourth layer of a hard polishing material, portions of said third layer of a soft polishing material, and said top surfaces of each of said one or more filled vias comprise said substantially planar surface.
Claim 2
Dependent Claim
166 words
A semiconductor device having a substantially planar top surface thereof, said device comprising: a substrate having a top surface thereof; raised features positioned on said top surface of said substrate; one or more filled vias extending upward from said raised features, each of said filled vias having a top surface thereof; a first layer of a soft polishing material overlying said top surface of said substrate and surrounding said one or more filled vias; a second layer of a hard polishing material overlying said first layer of a soft polishing material; a third layer of a soft polishing material overlying said second layer of a hard polishing material; and a conformal fourth layer of a hard polishing material overlying said third layer of a soft polishing material, wherein portions of said fourth layer of a hard polishing material, portions of said third layer of a soft polishing material, and said top surfaces of each of said one or more filled vias comprise said substantially planar surface.
Claim 3
Dependent Claim
13 words
The semiconductor device of claim 1 wherein said raised features comprise metal lines.
Claim 4
Dependent Claim
13 words
The semiconductor device of claim 1 wherein said filled vias comprise tungsten-filled vias.
Claim 5
Dependent Claim
17 words
The semiconductor device of claim 1, wherein said substantially planar surface varies to within about 750-1000 Angstroms.
Claim 6
Dependent Claim
37 words
The semiconductor device of claim 1, wherein at least one of the layers of hard polishing material comprises a material selected from the group consisting of silicon nitride, silicon carbide, diamond-like carbon, alumina, tungsten, and silicon dioxide.
Claim 7
Dependent Claim
14 words
The semiconductor device of claim 1, wherein the soft polishing material comprises a dielectric.
Claim 8
Dependent Claim
26 words
The semiconductor device of claim 6, wherein the dielectric is selected from the group consisting of silicon dioxide, phosphosilicate glass, borophosphosilicate glass, sputtered quartz, and polyimide.
References Cited (Backward Citations)
US3911562A
Cited
JPS5235980A
Cited
US4523372A
Cited
US4545852A
Cited
US4663832A
Cited
US4744862A
Cited
US4843033A
Cited
US4671851A
Cited
US4789648A
Cited
EP0223920A2
Cited
US4944836A
Cited
US4775550A
Cited
US4885261A
Cited
JPS63266830A
Cited
US4843034A
Cited
US4956313A
Cited
US4981550A
Cited
US4879257A
Cited
US4784721A
Cited
US4874464A
Cited
US5084419A
Cited
US4940509A
Cited
US4836885A
Cited
US4910155A
Cited
US4962063A
Cited
US4874463A
Cited
US4964946A
Cited
US5077234A
Cited
US5064683A
Cited
US5169491A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-23 | 1999-10-23 | 2000-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-23 | 2003-10-23 | 2004-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-23 | 2007-10-23 | 2008-04-23 | $7700.00 | Window Closed / Lapsed |