Method for outdiffusion of zinc into III-V substrates using zinc tungsten silicide as dopant source

Claim 1

A method of fabrication of self-aligned doped-region/contact structures in a semiconductor device, comprising the steps of: (a) forming metallic silicide and dopants over the surface of semiconductor material comprising elements of periodic table Groups III and V; and (b) diffusing some of said dopants into said semiconductor material.

Claim 2

A method of fabrication of self-aligned doped-region/contact structures in a semiconductor device, comprising the steps of: (a) forming metallic silicide and dopants over the surface of semiconductor material comprising elements of periodic table Groups III and V; and (b) diffusing some of said dopants into said semiconductor material.

Claim 5

A method of fabrication of junction field effect transistors, comprising the steps of: (a) forming metallic silicide and dopants over the surface of a semiconductor channel region; (b) patterning said silicide and dopants to define a junction gate location; (c) diffusing some of said dopants into said channel region to form the junction gate; and (d) forming source and drain contacts adjacent the channel region.

Claim 6

A method of fabrication of junction field effect transistors, comprising the steps of: (a) forming metallic silicide and dopants over the surface of a semiconductor channel region; (b) patterning said silicide and dopants to define a junction gate location; (c) diffusing some of said dopants into said channel region to form the junction gate; and (d) forming source and drain contacts adjacent the channel region.

Claim 9

A method of fabrication of a bipolar transistor, comprising the steps of: (a) forming a substrate with layer doped for the emitter, base, and collector at least said base comprising elements from periodic table Groups III and V; (b) depositing and patterning, to define the active area plus extrinsic base, an insulating and diffusion barrier on the emitter layer; (c) depositing a metallic silicide and a dopant on said insulating and diffusion barrier; (d) depositing an insulator on said metallic silicide and said dopant; (e) patterning and etching said insulator and combination to define the active area; (f) depositing a further insulating and diffusion barrier on said patterned insulator, exposed combination, and active area; (g) heating said combination to diffuse some of said dopants into said layers to form the extrinsic base and define the emitter; (h) anisotropically etching said further insulating and diffusion barrier to remove all of it except for sidewall portions on said exposed combination; and (i) depositing a contact for said emitter which is isolated from said combination by said sidewall portions and said insulator.

Claim 10

A method of fabrication of a bipolar transistor, comprising the steps of: (a) forming a substrate with layer doped for the emitter, base, and collector at least said base comprising elements from periodic table Groups III and V; (b) depositing and patterning, to define the active area plus extrinsic base, an insulating and diffusion barrier on the emitter layer; (c) depositing a metallic silicide and a dopant on said insulating and diffusion barrier; (d) depositing an insulator on said metallic silicide and said dopant; (e) patterning and etching said insulator and combination to define the active area; (f) depositing a further insulating and diffusion barrier on said patterned insulator, exposed combination, and active area; (g) heating said combination to diffuse some of said dopants into said layers to form the extrinsic base and define the emitter; (h) anisotropically etching said further insulating and diffusion barrier to remove all of it except for sidewall portions on said exposed combination; and (i) depositing a contact for said emitter which is isolated from said combination by said sidewall portions and said insulator.