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US4593457A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact

Assignee: NXP USA Inc
•
Filing: 1984-12-17
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Granted: 1986-06-10
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Expires: 2004-12-17
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Abstract

Abstract A gallium arsenide transistor is provided having a self-aligned base enhancement to emitter region and a method of applying metal to the emitter region. A series of steps provide an NPN structure overlying a substrate and includes an N region of aluminum gallium arsenide overlying a P base region for increasing the efficiency of the base-emitter junction by eliminating the need for a very heavily doped emitter at the surface of the chip. Two masking layers, one overlying the other, are deposited over the N emitter region and are patterned by known photoresist methods. The P base region is enhanced by implanting beryllium ions therein and partially into the N collector region. This ion implantation is blocked by the masking layers, creating a base enhancement region aligned with the emitter region. An etching process then undercuts the lower masking layer before the upper masking layer is removed. A photoresist is deposited on the surface and the lower masking layer is removed. Metal is deposited on the surface of the photoresist and the emitter region. The photoresist is then removed, thereby lifting off the metal thereon, leaving a metal contact on a portion of the emitter reigon.

Inventors

  • 👤 Mark S. Birrittella

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:23
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10P; H10P50/00; H10P50/69; H10P50/691; H10P76/00; H10P76/20; H10P76/202; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/084

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 133 words
A method for fabricating a binary III-V compound, self-aligned transistor device comprising the steps of: forming a first active layer having a first conductivity type overlying a substrate; forming a second active layer having a second conductivity type overlying said first active layer; forming a third active layer having said first conductivity type overlying said second active layer; forming a first masking layer overlying a portion of the surface of said third active layer; forming a second masking layer overlying said first masking layer selectively etching away said third active layer not underlying said first masking layer; and enhancing said second layer by implanting ions thereinto so that a portion of said first layer assumes a conductivity of said second type, said portion being aligned with but not underlying said first masking layer.
Claim 2
Independent Claim 133 words
A method for fabricating a binary III-V compound, self-aligned transistor device comprising the steps of: forming a first active layer having a first conductivity type overlying a substrate; forming a second active layer having a second conductivity type overlying said first active layer; forming a third active layer having said first conductivity type overlying said second active layer; forming a first masking layer overlying a portion of the surface of said third active layer; forming a second masking layer overlying said first masking layer selectively etching away said third active layer not underlying said first masking layer; and enhancing said second layer by implanting ions thereinto so that a portion of said first layer assumes a conductivity of said second type, said portion being aligned with but not underlying said first masking layer.
Claim 3
Dependent Claim 14 words
The method according to claim 1 wherein said enhancing step comprises implanting beryllium ions.
Claim 4
Dependent Claim 83 words
The method according to claim 1 further comprising the steps of: etching away a perpherial portion of said first masking layer by undercuting said second masking layer; etching away said second masking layer; forming a photoresist over said second layer and third layer and surrounding but not overlying said first masking layer; etching away said first masking layer; forming a metal on the portion of said third region within the opening left by etching away said first masking layer; and removing said photoresist.
Claim 5
Dependent Claim 17 words
The method according to claim 1 wherein said first, second and third active layers comprise gallium arsenide.
Claim 6
Dependent Claim 14 words
The method according to claim 1 wherein said first masking layer comprises silicon dioxide.
Claim 7
Dependent Claim 14 words
The method according to claim 2 wherein said metal comprises gold, germanium and nickel.
Claim 8
Dependent Claim 48 words
The method according to claim 3 wherein said forming a photoresist step comprises the steps of: forming a photoresist over said second layer, said third layer and said first masking layer; and etching a portion of said photoresist to expose the upper surface of said first masking layer.
Claim 9
Dependent Claim 31 words
The method according to claim 4 further comprising the step of forming a fourth active layer of aluminum gallium arsenide interposed between said second active layer and said third active layer.
Claim 10
Dependent Claim 14 words
The method according to claim 5 wherein said second masking layer comprises silicon nitride.

References Cited (Backward Citations)

US4380774A Cited
US4428111A Cited
US4494995A Cited
US4539743A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-06-09 1989-12-09 1990-06-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-06-09 1993-12-09 1994-06-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-06-09 1997-12-09 1998-06-10 $7700.00 Window Closed / Lapsed

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