Fully-differential amplifier

Claim 2

A differential amplifier, comprising: a first pair of PMOS and NMOS transistors coupled between a current source node and a current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to a first output terminal, and the gates of the PMOS and NMOS transistors are coupled to each other and to a first input terminal; a second pair of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other, and the gates of the PMOS and NMOS transistors are coupled to each other and to a second input terminal; an electronically controlled current source device coupled between a positive supply voltage and the current source node, the electronically controlled current source device having a control terminal adapted to receive a voltage to control the current flowing through the current source device; an electronically controlled current sink device coupled between a negative supply voltage and the current sink node, the electronically controlled current sink device having a control terminal adapted to receive a voltage to control the current flowing through the current sink device; a third pair of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to the control terminal of the current source device and the control terminal of the current sink device, and the gates of the PMOS and NMOS transistors are coupled to each other and to the first input terminal; and a fourth pair of PMOS and NMOS transistors coupled between the current source node and a current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to the control terminal of the current source device and the control terminal of the current sink device, and the gates of the PMOS and NMOS transistors are coupled to each other and to the second input terminal.

Claim 3

The differential amplifier of claim 1 wherein the current source device comprises a PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the third and fourth pairs, and the current sink device comprises an NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the third and fourth pairs.

Claim 4

The differential amplifier of claim 1 wherein the current sink device comprises: a first NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the third pair of transistors; and a second NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the fourth pair of transistors.

Claim 5

The differential amplifier of claim 1 wherein the current source device comprises: a first PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the third pair of transistors; and a second PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the fourth pair of transistors.

Claim 6

The differential amplifier of claim 4 wherein the current sink device comprises: a first NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the third pair of transistors; and a second NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the fourth pair of transistors.

Claim 7

The differential amplifier of claim 1 wherein the negative supply voltage comprises ground potential.

Claim 8

The differential amplifier of claim 1 wherein drains of the PMOS and NMOS transistors in the second pair are coupled to a second output terminal so that the first and second output terminals are differential output terminals.

Claim 9

A differential amplifier, comprising: a first amplifying circuit generating a first differential output signal from a first differential input signal; a second amplifying circuit generating a second differential output signal from a second differential input signal; and an internal bias circuit structured to internally bias the first and second amplifying circuits, the first amplifying circuit, the second amplifying circuit, and the internal bias circuit being entirely symmetrical at all circuit nodes.

Claim 10

A differential amplifier, comprising: a first amplifying circuit generating a first differential output signal from a first differential input signal; a second amplifying circuit generating a second differential output signal from a second differential input signal; and an internal bias circuit structured to internally bias the first and second amplifying circuits, the first amplifying circuit, the second amplifying circuit, and the internal bias circuit being entirely symmetrical at all circuit nodes.

Claim 11

The differential amplifier of claim 8 wherein: the first and second amplifying circuits comprise respective pairs of PMOS and NMOS transistors coupled between a current source node and a current sink node, in which the source of the PMOS transistor in each pair is coupled to the current source node, the source of the NMOS transistor in each pair is coupled to the current sink node, the drains of the PMOS and NMOS transistors in each pair are coupled to each other to generate a respective one of the differential output signals, and the gates of the PMOS and NMOS transistors in each pair are coupled to each other and coupled to receive a respective one of the differential input signals; and wherein the internal bias circuit comprises: first and second electronically controlled current devices coupled between respective positive and negative supply voltages and the current source and current sink nodes, respectively, the electronically controlled current devices each having a control terminal adapted to receive a voltage to control the current flowing through the current device; and respective pairs of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor in each pair is coupled to the current source node, the source of the NMOS transistor in each pair is coupled to the current sink node, the drains of the PMOS and NMOS transistors in each pair are coupled to the control terminals of the first and second electronically controlled current devices, and the gates of the PMOS and NMOS transistors in each pair are coupled to each other and coupled to receive a respective one of the differential input signals.

Claim 12

The differential amplifier of claim 9 wherein the first electronically controlled current device comprises a PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the pairs of transistors of the internal bias circuit, and wherein the second electronically controlled current device comprises an NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the pairs of transistors of the internal bias circuit.

Claim 13

The differential amplifier of claim 9 wherein the second electronically controlled current device comprises first and second NMOS transistors each having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 14

The differential amplifier of claim 9 wherein the first electronically controlled current device comprises first and second PMOS transistor each having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 15

The differential amplifier of claim 9 wherein: the first electronically controlled current device comprises first and second PMOS transistor each having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit; and the second electronically controlled current device comprises first and second NMOS transistors each having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 16

The differential amplifier of claim 9 wherein the negative supply voltage comprises ground potential.

Claim 17

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address; a control circuit adapted to receive a command from an external source and generate control signals responsive thereto to cause write data to be stored in and read data to be output from the memory cells of the at least one array; a read data path having a read register adapted to couple read data from the memory array to an externally accessible data terminal; a write data path having a write register adapted to couple write data from the externally accessible data terminal to the memory array; and a differential amplifier included in the register of at least one of the data paths to couple data signals between the externally accessible data terminal to the memory array, the differential amplifier comprising: a first pair of PMOS and NMOS transistors coupled between a current source node and a current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to a first output terminal, and the gates of the PMOS and NMOS transistors are coupled to each other and to a first input terminal; a second pair of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other, and the gates of the PMOS and NMOS transistors are coupled to each other and to a second input terminal; an electronically controlled current source device coupled between a positive supply voltage and the current source node, the electronically controlled current source device having a control terminal adapted to receive a voltage to control the current flowing through the current source device; an electronically controlled current sink device coupled between a negative supply voltage and the current sink node, the electronically controlled current sink device having a control terminal adapted to receive a voltage to control the current flowing through the current sink device; a third pair of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to the control terminal of the current source device and the control terminal of the current sink device, and the gates of the PMOS and NMOS transistors are coupled to each other and to the first input terminal; and a fourth pair of PMOS and NMOS transistors coupled between the current source node and a current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to the control terminal of the current source device and the control terminal of the current sink device, and the gates of the PMOS and NMOS transistors are coupled to each other and to the second input terminal.

Claim 18

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address; a control circuit adapted to receive a command from an external source and generate control signals responsive thereto to cause write data to be stored in and read data to be output from the memory cells of the at least one array; a read data path having a read register adapted to couple read data from the memory array to an externally accessible data terminal; a write data path having a write register adapted to couple write data from the externally accessible data terminal to the memory array; and a differential amplifier included in the register of at least one of the data paths to couple data signals between the externally accessible data terminal to the memory array, the differential amplifier comprising: a first pair of PMOS and NMOS transistors coupled between a current source node and a current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to a first output terminal, and the gates of the PMOS and NMOS transistors are coupled to each other and to a first input terminal; a second pair of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other, and the gates of the PMOS and NMOS transistors are coupled to each other and to a second input terminal; an electronically controlled current source device coupled between a positive supply voltage and the current source node, the electronically controlled current source device having a control terminal adapted to receive a voltage to control the current flowing through the current source device; an electronically controlled current sink device coupled between a negative supply voltage and the current sink node, the electronically controlled current sink device having a control terminal adapted to receive a voltage to control the current flowing through the current sink device; a third pair of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to the control terminal of the current source device and the control terminal of the current sink device, and the gates of the PMOS and NMOS transistors are coupled to each other and to the first input terminal; and a fourth pair of PMOS and NMOS transistors coupled between the current source node and a current sink node, in which the source of the PMOS transistor is coupled to the current source node, the source of the NMOS transistor is coupled to the current sink node, the drains of the PMOS and NMOS transistors are coupled to each other and to the control terminal of the current source device and the control terminal of the current sink device, and the gates of the PMOS and NMOS transistors are coupled to each other and to the second input terminal.

Claim 19

The memory device of claim 15 wherein the current source device comprises a PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the third and fourth pairs, and the current sink device comprises an NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the third and fourth pairs.

Claim 20

The memory device of claim 15 wherein the current sink device comprises: a first NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the third pair of transistors; and a second NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the fourth pair of transistors.

Claim 21

The memory device of claim 15 wherein the current source device comprises: a first PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the third pair of transistors; and a second PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the fourth pair of transistors.

Claim 22

The memory device of claim 18 wherein the current sink device comprises: a first NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the third pair of transistors; and a second NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the fourth pair of transistors.

Claim 23

The memory device of claim 15 wherein the negative supply voltage comprises ground potential.

Claim 24

The memory device of claim 15 wherein drains of the PMOS and NMOS transistors in the second pair are coupled to a second output terminal so that the first and second output terminals are differential output terminals.

Claim 25

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address; a control circuit adapted to receive a command from an external source and generate control signals responsive thereto to cause write data to be stored in and read data to be output from the memory cells of the at least one array; a read data path having a read register adapted to couple read data from the memory array to an externally accessible data terminal; a write data path having a write register adapted to couple write data from the externally accessible data terminal to the memory array; and a differential amplifier included in the register of at least one of the data paths to couple data signals between the externally accessible data terminal to the memory array, the differential amplifier comprising: a first amplifying circuit generating a first differential output signal from a first differential input signal; a second amplifying circuit generating a second differential output signal from a second differential input signal; and an internal bias circuit structured to internally bias the first and second amplifying circuits, the first amplifying circuit, the second amplifying circuit, and the internal bias circuit being entirely symmetrical at all circuit nodes.

Claim 26

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address; a control circuit adapted to receive a command from an external source and generate control signals responsive thereto to cause write data to be stored in and read data to be output from the memory cells of the at least one array; a read data path having a read register adapted to couple read data from the memory array to an externally accessible data terminal; a write data path having a write register adapted to couple write data from the externally accessible data terminal to the memory array; and a differential amplifier included in the register of at least one of the data paths to couple data signals between the externally accessible data terminal to the memory array, the differential amplifier comprising: a first amplifying circuit generating a first differential output signal from a first differential input signal; a second amplifying circuit generating a second differential output signal from a second differential input signal; and an internal bias circuit structured to internally bias the first and second amplifying circuits, the first amplifying circuit, the second amplifying circuit, and the internal bias circuit being entirely symmetrical at all circuit nodes.

Claim 27

The memory device of claim 22 wherein: the first and second amplifying circuits comprise respective pairs of PMOS and NMOS transistors coupled between a current source node and a current sink node, in which the source of the PMOS transistor in each pair is coupled to the current source node, the source of the NMOS transistor in each pair is coupled to the current sink node, the drains of the PMOS and NMOS transistors in each pair are coupled to each other to generate a respective one of the differential output signals, and the gates of the PMOS and NMOS transistors in each pair are coupled to each other and coupled to receive a respective one of the differential input signals; and wherein the internal bias circuit comprises: first and second electronically controlled current devices coupled between respective positive and negative supply voltages and the current source and current sink nodes, respectively, the electronically controlled current devices each having a control terminal adapted to receive a voltage to control the current flowing through the current device; and respective pairs of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor in each pair is coupled to the current source node, the source of the NMOS transistor in each pair is coupled to the current sink node, the drains of the PMOS and NMOS transistors in each pair are coupled to the control terminals of the first and second electronically controlled current devices, and the gates of the PMOS and NMOS transistors in each pair are coupled to each other and coupled to receive a respective one of the differential input signals.

Claim 28

The memory device of claim 23 wherein the first electronically controlled current device comprises a PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the pairs of transistors of the internal bias circuit, and wherein the second electronically controlled current device comprises an NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the pairs of transistors of the internal bias circuit.

Claim 29

The memory device of claim 23 wherein the second electronically controlled current device comprises first and second NMOS transistors each having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 30

The memory device of claim 23 wherein the first electronically controlled current device comprises first and second PMOS transistor each having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 31

The memory device of claim 23 wherein: the first electronically controlled current device comprises first and second PMOS transistor each having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit; and the second electronically controlled current device comprises first and second NMOS transistors each having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 32

The memory device of claim 23 wherein the negative supply voltage comprises ground potential.

Claim 33

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; a memory controller coupled to the processor through the processor bus; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address; a control circuit adapted to receive a command from an external source and generate control signals responsive thereto to cause write data to be stored in and read data to be output from the memory cells of the at least one array; a read data path having a read register adapted to couple read data from the memory array to an externally accessible data terminal; a write data path having a write register adapted to couple write data from the externally accessible data terminal to the memory array; and a differential amplifier included in the register of at least one of the data paths to couple data signals between the externally accessible data terminal to the memory array, the differential amplifier comprising: a first amplifying circuit generating a first differential output signal from a first differential input signal; a second amplifying circuit generating a second differential output signal from a second differential input signal; and an internal bias circuit structured to internally bias the first and second amplifying circuits, the first amplifying circuit, the second amplifying circuit, and the internal bias circuit being entirely symmetrical at all circuit nodes.

Claim 34

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; a memory controller coupled to the processor through the processor bus; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address; a control circuit adapted to receive a command from an external source and generate control signals responsive thereto to cause write data to be stored in and read data to be output from the memory cells of the at least one array; a read data path having a read register adapted to couple read data from the memory array to an externally accessible data terminal; a write data path having a write register adapted to couple write data from the externally accessible data terminal to the memory array; and a differential amplifier included in the register of at least one of the data paths to couple data signals between the externally accessible data terminal to the memory array, the differential amplifier comprising: a first amplifying circuit generating a first differential output signal from a first differential input signal; a second amplifying circuit generating a second differential output signal from a second differential input signal; and an internal bias circuit structured to internally bias the first and second amplifying circuits, the first amplifying circuit, the second amplifying circuit, and the internal bias circuit being entirely symmetrical at all circuit nodes.

Claim 35

The computer system of claim 29 wherein: the first and second amplifying circuits comprise respective pairs of PMOS and NMOS transistors coupled between a current source node and a current sink node, in which the source of the PMOS transistor in each pair is coupled to the current source node, the source of the NMOS transistor in each pair is coupled to the current sink node, the drains of the PMOS and NMOS transistors in each pair are coupled to each other to generate a respective one of the differential output signals, and the gates of the PMOS and NMOS transistors in each pair are coupled to each other and coupled to receive a respective one of the differential input signals; and wherein the internal bias circuit comprises: first and second electronically controlled current devices coupled between respective positive and negative supply voltages and the current source and current sink nodes, respectively, the electronically controlled current devices each having a control terminal adapted to receive a voltage to control the current flowing through the current device; and respective pairs of PMOS and NMOS transistors coupled between the current source node and the current sink node, in which the source of the PMOS transistor in each pair is coupled to the current source node, the source of the NMOS transistor in each pair is coupled to the current sink node, the drains of the PMOS and NMOS transistors in each pair are coupled to the control terminals of the first and second electronically controlled current devices, and the gates of the PMOS and NMOS transistors in each pair are coupled to each other and coupled to receive a respective one of the differential input signals.

Claim 36

The computer system of claim 30 wherein the first electronically controlled current device comprises a PMOS transistor having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in the pairs of transistors of the internal bias circuit, and wherein the second electronically controlled current device comprises an NMOS transistor having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in the pairs of transistors of the internal bias circuit.

Claim 37

The computer system of claim 30 wherein the second electronically controlled current device comprises first and second NMOS transistors each having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 38

The computer system of claim 30 wherein the first electronically controlled current device comprises first and second PMOS transistor each having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 39

The computer system of claim 30 wherein: the first electronically controlled current device comprises first and second PMOS transistor each having its source coupled to the positive supply voltage, its drain coupled to the current source node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit; and the second electronically controlled current device comprises first and second NMOS transistors each having its source coupled to the negative supply voltage, its drain coupled to the current sink node, and its gate coupled to the drains of the transistors in a respective pair of the transistors of the internal bias circuit.

Claim 40

The computer system of claim 30 wherein the negative supply voltage comprises ground potential.