US4459660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU
Assignee: Texas Instruments Inc
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Filing: 1981-04-13
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Granted: 1984-07-10
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Expires: 2001-04-13
Abstract
Abstract A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.
Inventors
- 👤 Jeffrey D. Bellay
- 👤 Michael J. Hogan
- 👤 Kevin C. McDonough
- 👤 John W. Hayn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:53
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/786; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
135 words
A microprocessor device comprising: a CPU formed in a semiconductor body and operating in a machine cycle, and a memory including rows and columns of cells formed in said body, the CPU generating addresses for coupling to said memory, the memory being of the type requiring refresh within a given time period, a refresh address generator for generating addresses for coupling to said memory, addressing means for coupling to the memory every machine cycle one of said addresses from the CPU or one of said addresses from the refresh address generator, means for incrementing the refresh address generator every machine cycle only if an address from the refresh address generator is coupled to the memory, the machine cycle being less than said given time period divided by the number of said rows in the memory.
Claim 2
Dependent Claim
135 words
A microprocessor device comprising: a CPU formed in a semiconductor body and operating in a machine cycle, and a memory including rows and columns of cells formed in said body, the CPU generating addresses for coupling to said memory, the memory being of the type requiring refresh within a given time period, a refresh address generator for generating addresses for coupling to said memory, addressing means for coupling to the memory every machine cycle one of said addresses from the CPU or one of said addresses from the refresh address generator, means for incrementing the refresh address generator every machine cycle only if an address from the refresh address generator is coupled to the memory, the machine cycle being less than said given time period divided by the number of said rows in the memory.
Claim 3
Dependent Claim
31 words
A device according to claim 1 wherein the address from the CPU includes a row and column address and the address from the refresh address generator includes only a row address.
Claim 4
Dependent Claim
139 words
A microprocessor device comprising: a CPU formed in a semiconductor body and operating in a machine cycle, and a memory including N rows of one-transistor dynamic storage cells formed in said body and accessed by the CPU by row and column address, the memory being of the type requiring refresh within a given time period, a refresh address generator for generating addresses only of said rows, addressing means for accessing the memory every machine cycle based on a row and column address from the CPU or a row address from the refresh address generator, means for incrementing the refresh address generator every machine cycle if the CPU does not access the memory, wherein the refresh address generator is not incremented if the CPU accesses the memory, the machine cycle being less than said given time period divided by N.
Claim 5
Dependent Claim
139 words
A microprocessor device comprising: a CPU formed in a semiconductor body and operating in a machine cycle, and a memory including N rows of one-transistor dynamic storage cells formed in said body and accessed by the CPU by row and column address, the memory being of the type requiring refresh within a given time period, a refresh address generator for generating addresses only of said rows, addressing means for accessing the memory every machine cycle based on a row and column address from the CPU or a row address from the refresh address generator, means for incrementing the refresh address generator every machine cycle if the CPU does not access the memory, wherein the refresh address generator is not incremented if the CPU accesses the memory, the machine cycle being less than said given time period divided by N.
Claim 6
Dependent Claim
21 words
A device according to claim 3 wherein a bistable sense/refresh amplifier is connected to the center of each column of cells.
Claim 7
Independent Claim
179 words
A method of operating a microcomputer system; said microcomputer system having an arithmetic/logic unit, a plurality of data/address registers, an instruction register, a read-only memory, and a read/write memory; and said microcomputer system having data/address bus means for accessing the arithmetic/logic unit, the data/address registers, the instruction register, the read-only memory and the read/write memory; the sytem having a microinstruction memory means for addressing the microinstruction memory coupled to the instruction register; comprising the steps of: (a) clocking said system to access the read-only or read/write memory, to access the microinstruction memory and to operate the arithmetic/logic unit, in a repetitive machine state, (b) generating a first address in a refresh address counter, (c) generating a second address in one of said data/address registers, (d) generating a third address in another of said data/address registers, (e) applying an address to said read-only memory via said bus means to access a program instruction for loading in said instruction register, (f) and selecting between said first and second addresses for applying an address to the read/write memory during every machine state.
Claim 8
Independent Claim
179 words
A method of operating a microcomputer system; said microcomputer system having an arithmetic/logic unit, a plurality of data/address registers, an instruction register, a read-only memory, and a read/write memory; and said microcomputer system having data/address bus means for accessing the arithmetic/logic unit, the data/address registers, the instruction register, the read-only memory and the read/write memory; the sytem having a microinstruction memory means for addressing the microinstruction memory coupled to the instruction register; comprising the steps of: (a) clocking said system to access the read-only or read/write memory, to access the microinstruction memory and to operate the arithmetic/logic unit, in a repetitive machine state, (b) generating a first address in a refresh address counter, (c) generating a second address in one of said data/address registers, (d) generating a third address in another of said data/address registers, (e) applying an address to said read-only memory via said bus means to access a program instruction for loading in said instruction register, (f) and selecting between said first and second addresses for applying an address to the read/write memory during every machine state.
Claim 9
Dependent Claim
26 words
A method according to claim 5 including the step of incrementing said refresh address counter during each machine cycle except when the second address is selected.
Claim 10
Dependent Claim
18 words
A method according to claim 5 wherein said second address is selected in response to the content thereof.
Claim 11
Dependent Claim
18 words
A method according to claim 7 wherein said second address is selected when said read-only memory is accessed.
Claim 12
Dependent Claim
23 words
A method according to claim 8 wherein said read/write memory has a maximum refresh time and said counter repeats within said refresh time.
References Cited (Backward Citations)
US4332008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-10 | 1988-01-09 | 1988-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-10 | 1992-01-09 | 1992-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-10 | 1996-01-09 | 1996-07-10 | $7700.00 | Window Closed / Lapsed |