Layout for a semiconductor memory device having redundant elements

Claim 2

A semiconductor device having a plurality of primary circuit elements addressable based on an external address word, wherein some of the primary circuit elements can be defective, the semiconductor device comprising: a plurality of fuse banks for storing addresses of defective circuit elements in the plurality of primary circuit elements; at least one comparison circuit coupled to receive the external address word and the stored addresses of the plurality of fuse banks, the comparison circuit comparing the external address word to the stored addresses and outputting a match signal if the external address word and one of the stored addresses correlate; at least one switching circuit coupled between the comparison circuit and the plurality of fuse banks, the switching circuit selecting one of the plurality of fuse banks to couple to the comparison circuit based on the external address word; a plurality of redundant circuit elements, each of which corresponds to one of the fuse banks, the plurality of redundant circuit elements capable of substituting for defective circuit elements in the plurality of primary circuit elements; and control and addressing circuitry coupled to the comparison circuit and the plurality of primary and redundant circuit elements, the control and addressing circuitry receiving the match signal and accessing a one of the redundant memory elements that corresponds to the one fuse bank selected by the switching circuit.

Claim 3

The semiconductor device of claim 1 wherein the plurality of primary and redundant circuit elements and the plurality of fuse banks are each divided into first and second sets, wherein the control and addressing circuit receives the external address word and decodes it to provide a decoded address word, and wherein the switching circuit selects one of the first and second fuse banks to couple to the comparison circuit based on a bit in the decoded address word.

Claim 4

The semiconductor device of claim 1 wherein the plurality of primary and redundant circuit elements are divided into at least first and second sets, wherein the semiconductor memory device further includes a plurality of sense amplifiers coupled to and shared between the first and second sets of primary and redundant circuit elements, and further including a plurality of isolation gates coupled between the first and second sets of primary and redundant circuit elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of primary and redundant circuit elements when the second or first set of primary and redundant circuit elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers.

Claim 5

The semiconductor device of claim 1 wherein the at least one switching circuit is a 2:1 multiplexing circuit coupled to first and second fuse banks.

Claim 6

The semiconductor device of claim 1, further comprising a number of electrically conductive match lines coupled between the comparison circuit and the control and addressing circuitry, wherein the plurality of redundant circuit elements are divided into at least a plurality of columns, and wherein the number of electrically conductive match lines is less than a number of the plurality of columns of redundant circuit elements.

Claim 7

The semiconductor device of claim 1 wherein the plurality of primary and redundant circuit elements are memory elements, wherein the comparison circuit includes at least one exclusive OR gate, and wherein the switching element includes a 2:1 multiplexing circuit.

Claim 8

A semiconductor memory device, comprising: a plurality of primary memory elements and a plurality of redundant memory elements, the plurality of primary memory elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of primary and redundant memory elements being divided into at least first and second sets, wherein the first set of redundant memory elements can substitute for defective memory elements in the first set of primary memory elements and the second set of redundant memory elements can substitute for defective memory elements in the second set of primary memory elements, and wherein the redundant memory elements are divided into at least a plurality of columns; a plurality of sense amplifiers coupled to and shared between the first and second sets of primary and redundant memory elements; a plurality of isolation gates coupled between the first and second sets of primary and redundant memory elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of primary and redundant memory elements when the second or first set of primary and redundant memory elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers; control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary memory elements based on the external address word supplied thereto; at least first and second sets of fuse banks for storing addresses of defective memory elements in the first and second sets of primary memory elements, respectively; a number of electrically conductive match lines equal to a number of columns of redundant memory elements in the first set of redundant memory elements, the match lines being coupled to both the first and second sets of redundant memory elements; at least one comparison circuit coupled to the control and addressing circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a match signal, on one of the lines, to access one of the columns of redundant memory elements if the address word and one of the stored addresses correlate; and at least one multiplexing circuit coupled between the comparison circuit and the first and second fuse banks, the multiplexing circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse banks to couple to the comparison circuit.

Claim 9

A semiconductor memory device, comprising: a plurality of primary memory elements and a plurality of redundant memory elements, the plurality of primary memory elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of primary and redundant memory elements being divided into at least first and second sets, wherein the first set of redundant memory elements can substitute for defective memory elements in the first set of primary memory elements and the second set of redundant memory elements can substitute for defective memory elements in the second set of primary memory elements, and wherein the redundant memory elements are divided into at least a plurality of columns; a plurality of sense amplifiers coupled to and shared between the first and second sets of primary and redundant memory elements; a plurality of isolation gates coupled between the first and second sets of primary and redundant memory elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of primary and redundant memory elements when the second or first set of primary and redundant memory elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers; control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary memory elements based on the external address word supplied thereto; at least first and second sets of fuse banks for storing addresses of defective memory elements in the first and second sets of primary memory elements, respectively; a number of electrically conductive match lines equal to a number of columns of redundant memory elements in the first set of redundant memory elements, the match lines being coupled to both the first and second sets of redundant memory elements; at least one comparison circuit coupled to the control and addressing circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a match signal, on one of the lines, to access one of the columns of redundant memory elements if the address word and one of the stored addresses correlate; and at least one multiplexing circuit coupled between the comparison circuit and the first and second fuse banks, the multiplexing circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse banks to couple to the comparison circuit.

Claim 10

The semiconductor memory device of claim 7 wherein the redundant memory elements are divided into a plurality of rows and the plurality of columns, wherein a number of fuse banks in the first and second sets of fuse banks is equal to a number of redundant rows and columns, wherein one comparison circuit is coupled to every four fuse banks in the first and second sets of fuse banks, wherein a first two of every four fuse banks provide addresses corresponding to redundant rows and columns in the first set and a second two of every four fuse banks provide addresses corresponding to redundant rows and columns in the second set, wherein a first group of 2:1 multiplexing circuits is coupled to the first two of every four fuse banks, a second group of 2:1 multiplexing circuits is coupled to the second two of every four fuse banks, and a third group of 2:1 multiplexing circuits is coupled to the first and second multiplexing circuits, wherein each fuse bank in the first and second set of fuse banks has a number of fuses equal to at least the predetermined bit length of the external address word and, wherein a number of multiplexing circuits in the first, second and third groups of multiplexing circuits is equal to a number of bits in the predetermined bit length.

Claim 11

The semiconductor memory device of claim 7 wherein the redundant memory elements are divided into a plurality of rows and the plurality of columns, and wherein a number of fuse banks in the first and second sets of fuse banks equals a number of redundant rows and columns.

Claim 12

The semiconductor memory device of claim 7 wherein the redundant memory elements are divided into a plurality of rows and the plurality of columns, wherein a first two of every four fuse banks provide addresses corresponding to redundant rows and columns in the first set and a second two of every four fuse banks provide addresses corresponding to redundant rows and columns in the second set, and wherein a first multiplexing circuit is coupled to the first two of every four fuse banks, a second multiplexing circuit is coupled to the second two of every four fuse banks, and a third multiplexing circuit is coupled to the first and second multiplexing circuits.

Claim 13

The semiconductor memory device of claim 7, further comprising a plurality of row and column decoders coupled to the first and second sets of memory elements, and wherein the match lines are coupled to each of the row and column decoders.

Claim 14

The semiconductor memory device of claim 7 wherein the comparison circuit includes: at least one exclusive OR gate that is coupled to receive at its inputs the external address word and the stored address in either the first or second fuse banks, and outputting a correlation signal if the external address word and the stored address correlate, an enable circuit coupled to the first and second fuse banks and outputting an enable signal if the first or second fuse banks are enabled, and a NAND gate that is coupled to receive the correlation signal and the enable signal at its inputs, and outputting the match signal to one of the match lines in response to both the correlation and enable signals.

Claim 15

A semiconductor device, comprising: a plurality of primary and redundant circuit elements, the plurality of primary circuit elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of primary and redundant circuit elements being divided into at least first and second sets wherein circuit elements in the first and second sets are not simultaneously active, wherein the first and second sets of redundant circuit elements can substitute for defective circuit elements in the first and second sets of primary circuit elements, respectively, and wherein the redundant circuit elements are divided into at least a plurality of columns; control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary circuit elements based on the external address word supplied thereto; at least first and second sets of fuse banks for storing addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively; at least one comparison circuit coupled to the control and addressing circuitry and the first and second sets of circuit elements, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a match signal to access one of the columns of redundant circuit elements if the address word and one of the stored addresses correlate; and at least one gating circuit coupled between the comparison circuit and the first and second fuse banks, the gating circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse banks to couple to the comparison circuit.

Claim 16

A semiconductor device, comprising: a plurality of primary and redundant circuit elements, the plurality of primary circuit elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length, the plurality of primary and redundant circuit elements being divided into at least first and second sets wherein circuit elements in the first and second sets are not simultaneously active, wherein the first and second sets of redundant circuit elements can substitute for defective circuit elements in the first and second sets of primary circuit elements, respectively, and wherein the redundant circuit elements are divided into at least a plurality of columns; control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary circuit elements based on the external address word supplied thereto; at least first and second sets of fuse banks for storing addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively; at least one comparison circuit coupled to the control and addressing circuitry and the first and second sets of circuit elements, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a match signal to access one of the columns of redundant circuit elements if the address word and one of the stored addresses correlate; and at least one gating circuit coupled between the comparison circuit and the first and second fuse banks, the gating circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse banks to couple to the comparison circuit.

Claim 17

The semiconductor device of claim 13, further comprising: a plurality of sense amplifiers coupled to and shared between the first and second sets of circuit elements; a plurality of isolation gates coupled between the first and second sets of circuit elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of circuit elements when the second or first set of circuit elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers so that circuit elements in the first and second sets are not simultaneously active.

Claim 18

The semiconductor device of claim 13, further comprising a number of electrically conductive match lines equal to a number of columns of redundant circuit elements in the first set of redundant circuit elements, the match lines being coupled to both the first and second sets of redundant circuit elements and to the comparison circuit, and wherein the redundant circuit elements are divided into a plurality of rows and the plurality of columns, wherein a number of fuse banks in the first and second sets of fuse banks is equal to a number of redundant rows and columns, wherein one comparison circuit is coupled to every four fuse banks in the first and second sets of fuse banks, wherein a first two of every four fuse banks provide addresses corresponding to redundant rows and columns in the first set and a second two of every four fuse banks provide addresses corresponding to redundant rows and columns in the second set, wherein the gate circuit comprises a plurality of multiplexing circuits wherein a first group of multiplexing circuits is coupled to the first two of every four fuse banks, a second group of multiplexing circuits is coupled to the second two of every four fuse banks, and a third group of multiplexing circuits is coupled to the first and second multiplexing circuits, wherein each fuse bank in the first and second set of fuse banks has a number of fuses equal to at least the predetermined bit length of the external address word and, wherein a number of multiplexing circuits in the first, second and third groups of multiplexing circuits is equal to a number of bits in the predetermined bit length.

Claim 19

The semiconductor circuit device of claim 13 wherein the redundant circuit elements are divided into a plurality of rows and columns, wherein a number of fuse banks in the first and second sets of fuse banks equals a number of redundant rows and columns, and wherein the circuit elements are memory cells.

Claim 20

The semiconductor circuit device of claim 13 wherein the redundant circuit elements are divided into a plurality of rows and the plurality of columns, wherein a first two of every four fuse banks provide addresses corresponding to redundant rows and columns in the first set and a second two of every four fuse banks provide addresses corresponding to redundant rows and columns in the second set, wherein the gating circuit includes a plurality of multiplexing circuits, and wherein a first multiplexing circuit is coupled to the first two of every four fuse banks, a second multiplexing circuit is coupled to the second two of every four fuse banks, and a third multiplexing circuit is coupled to the first and second multiplexing circuits.

Claim 21

The semiconductor circuit device of claim 13 wherein comparison circuit includes: at least one exclusive OR gate that is coupled to receive at its inputs the external address word and the stored address in either the first or second fuse banks, and outputting a correlation signal if the external address word and the stored address correlate, an enable circuit coupled to the first and second fuse banks and outputting an enable signal if the first or second fuse banks are enabled, and a NAND gate that is coupled to receive the correlation signal and the enable signal at its inputs, and outputting the match signal in response to both the correlation and enable signals.

Claim 22

A computer system comprising: an input device; an output device; an address bus; a data bus; a set of control lines; a memory controller coupled to the address and data buses and to the set of control lines; a processor coupled to the input and output devices, to the address and data buses and to the set of control lines; and a memory device coupled to the memory controller through the address and data buses and the set of control lines, the memory device comprising: a plurality of primary and redundant memory elements, the plurality of primary memory elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length from the address bus, the plurality of primary and redundant memory elements being divided into at least first and second sets, wherein the first and second sets of redundant memory elements can substitute for defective memory elements in the first and second sets of primary memory elements, respectively, and wherein the redundant memory elements are divided into at least a plurality of columns; a plurality of sense amplifiers coupled to and shared between the first and second sets of memory elements; a plurality of isolation gates coupled between the first and second sets of memory elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of memory elements when the second or first set of memory elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers; control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary memory elements based on the external address word supplied thereto; at least first and second sets of fuse banks for storing addresses of defective memory elements in the first and second sets of primary memory elements, respectively; a number of electrically conductive match lines equal to a number of columns of redundant memory elements in the first set of redundant memory elements, the match lines being coupled to both the first and second sets of redundant memory elements; at least one comparison circuit coupled to the control and addressing circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a match signal to the control and addressing circuitry, on one of the lines, to access one of the columns of redundant memory elements if the address word and one of the stored addresses correlate; and at least one multiplexing circuit coupled between the comparison circuit and the first and second fuse banks, the multiplexing circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse banks to couple to the comparison circuit.

Claim 23

A computer system comprising: an input device; an output device; an address bus; a data bus; a set of control lines; a memory controller coupled to the address and data buses and to the set of control lines; a processor coupled to the input and output devices, to the address and data buses and to the set of control lines; and a memory device coupled to the memory controller through the address and data buses and the set of control lines, the memory device comprising: a plurality of primary and redundant memory elements, the plurality of primary memory elements being addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length from the address bus, the plurality of primary and redundant memory elements being divided into at least first and second sets, wherein the first and second sets of redundant memory elements can substitute for defective memory elements in the first and second sets of primary memory elements, respectively, and wherein the redundant memory elements are divided into at least a plurality of columns; a plurality of sense amplifiers coupled to and shared between the first and second sets of memory elements; a plurality of isolation gates coupled between the first and second sets of memory elements and the shared sense amplifiers, the isolation gates disabling either the first or second set of memory elements when the second or first set of memory elements, respectively, is actively coupled to at least one of the plurality of shared sense amplifiers; control and addressing circuitry coupled to the electrically conductive row and column lines for permitting communication with the plurality of primary memory elements based on the external address word supplied thereto; at least first and second sets of fuse banks for storing addresses of defective memory elements in the first and second sets of primary memory elements, respectively; a number of electrically conductive match lines equal to a number of columns of redundant memory elements in the first set of redundant memory elements, the match lines being coupled to both the first and second sets of redundant memory elements; at least one comparison circuit coupled to the control and addressing circuitry and the match lines, the comparison circuit comparing the external address word to the stored addresses in either the first or second fuse banks and outputting a match signal to the control and addressing circuitry, on one of the lines, to access one of the columns of redundant memory elements if the address word and one of the stored addresses correlate; and at least one multiplexing circuit coupled between the comparison circuit and the first and second fuse banks, the multiplexing circuit receiving at least one bit of the address word and selecting, based thereon, one of the first and second fuse banks to couple to the comparison circuit.

Claim 24

The computer of claim 19 wherein the redundant memory elements are divided into a plurality of rows and the plurality of columns, wherein a first two of every four fuse banks provide addresses corresponding to redundant rows and columns in the first set and a second two of every four fuse banks provide addresses corresponding to redundant rows and columns in the second set, and wherein a first multiplexing circuit is coupled to the first two of every four fuse banks, a second multiplexing circuit is coupled to the second two of every four fuse banks, and a third multiplexing circuit is coupled to the first and second multiplexing circuits.

Claim 25

The computer of claim 19 wherein comparison circuit includes: at least one exclusive OR gate that is coupled to receive at its inputs the external address word and the stored address in either the first or second fuse banks, and outputting a correlation signal if the external address word and the stored address correlate, an enable circuit coupled to the first and second fuse banks and outputting an enable signal if the first or second fuse banks are enabled, and a NAND gate that is coupled to receive the correlation signal and the enable signal at its inputs, and outputting the match signal to one of the match lines in response to both the correlation and enable signals.