Process for fabricating DRAM capacitor

Claim 1

A process of fabricating a storage capacitor of a dynamic random access memory of an integrated circuit comprising the steps of: forming an insulating layer over a surface of a substrate of the integrated circuit, the substrate comprising a metal-oxide semiconductor transistor for a dynamic random access cell unit of the integrated circuit, with a contact opening formed in the insulating layer revealing a surface of a source/drain region of the transistor; forming a conductive layer covering a surface of the insulating layer and an exposed surface of the source/drain region inside the contact opening, the conductive layer being patterned into a shape for a bottom electrode of the storage capacitor exposing the surface of the insulating layer; forming an amorphous silicon layer covering the surface of the conductive layer and the exposed surface of the insulating layer; forming a hemispherical-grain silicon layer covering a surface of the electrode comprising the patterned conductive layer, a course top surface and a sidewall covered by the amorphous silicon layer and the hemispherical-grain silicon layer is formed; removing portions of the hemispherical-grain silicon layer and portions of the amorphous silicon layer not designated for the bottom electrode of the storage capacitor; and forming a dielectric layer and a top electrode of the storage capacitor on the dielectric layer.

Claim 16

A method for forming a storage capacitor of a dynamic random access memory, comprising: providing a substrate having a metal-oxide semiconductor which comprises a source/drain region in the substrate; forming an insulating layer with a contact opening exposing the source/drain region; forming a patterned conductive layer to cover a portion of the insulating layer and to fill the contact opening; forming an amorphous silicon layer to cover the patterned conductive layer and the insulating layer uncovered by the patterned conductive layer; forming a hemispherical-grain silicon layer to cover the amorphous layer with a native oxide layer thereon; removing the native oxide layer; and removing portions of the hemispherical-grain silicon layer and portions of the amorphous silicon layer.

Claim 17

A method for forming a storage capacitor of a dynamic random access memory, comprising: providing a substrate having a metal-oxide semiconductor which comprises a source/drain region in the substrate; forming an insulating layer with a contact opening exposing the source/drain region; forming a patterned conductive layer to cover a portion of the insulating layer and to fill the contact opening; forming an amorphous silicon layer to cover the patterned conductive layer and the insulating layer uncovered by the patterned conductive layer; forming a hemispherical-grain silicon layer to cover the amorphous layer with a native oxide layer thereon; removing the native oxide layer; and removing portions of the hemispherical-grain silicon layer and portions of the amorphous silicon layer.