Method of making capacitor of highly integrated semiconductor device using multiple insulation layers

Claim 1

A method for manufacturing a capacitor of a highly integrated semiconductor device, comprising the steps of: (a) successively forming on a semiconductor substrate first, second and third insulation layer patterns, a metal layer pattern and a fourth insulation layer pattern and forming a contact hole for exposing a region of said semiconductor substrate therein; (b) forming a spacer on the sidewalls of said contact hole; (c) forming a conductive layer for completely filling said contact hole on the whole surface of the resultant structure from said step (b); (d) forming a photoresist pattern on the conductive layer over the contact hole; (e) forming a conductive layer pattern for exposing said metal layer pattern around said contact hole and deformed fourth insulation layer patterns by sequentially etching said conductive layer and said fourth insulation layer using said photoresist pattern as an etching mask; (f) removing said photoresist pattern; (g) depositing an HSG (hemispherical grain) polysilicon layer on the whole surface of the resultant structure from said step (f); (h) forming a metal silicide layer between said deformed fourth insulation layer patterns by reacting said exposed metal layer with said HSG polysilicon layer thereon; and (i) removing said metal silicide layer with a chemical solution, thereby forming a storage electrode consisting of said conductive layer pattern and said HSG polysilicon layer formed on the top and side surface of said conductive layer pattern.

Claim 2

A method for manufacturing a capacitor of a highly integrated semiconductor device, comprising the steps of: (a) successively forming on a semiconductor substrate first, second and third insulation layer patterns, a metal layer pattern and a fourth insulation layer pattern and forming a contact hole for exposing a region of said semiconductor substrate therein; (b) forming a spacer on the sidewalls of said contact hole; (c) forming a conductive layer for completely filling said contact hole on the whole surface of the resultant structure from said step (b); (d) forming a photoresist pattern on the conductive layer over the contact hole; (e) forming a conductive layer pattern for exposing said metal layer pattern around said contact hole and deformed fourth insulation layer patterns by sequentially etching said conductive layer and said fourth insulation layer using said photoresist pattern as an etching mask; (f) removing said photoresist pattern; (g) depositing an HSG (hemispherical grain) polysilicon layer on the whole surface of the resultant structure from said step (f); (h) forming a metal silicide layer between said deformed fourth insulation layer patterns by reacting said exposed metal layer with said HSG polysilicon layer thereon; and (i) removing said metal silicide layer with a chemical solution, thereby forming a storage electrode consisting of said conductive layer pattern and said HSG polysilicon layer formed on the top and side surface of said conductive layer pattern.