US5936977A
Expired / Lapsed
US
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Scan path circuitry including a programmable delay circuit
Assignee: Monterey Research LLC
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Filing: 1997-09-17
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Granted: 1999-08-10
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Expires: 2017-09-17
Abstract
Abstract A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.
Inventors
- 👤 Jonathan F. Churchill
- 👤 Neil P. Raftery
- 👤 Colin J. Hendry
- 👤 Jeyakumar Shanmugam
- 👤 Mark A. Finn
- 👤 Thomas M. Surrette
- 👤 Cathal G. Phelan
- 👤 Ashish Pancholy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/31858
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
54 words
A circuit for delaying a signal comprising: a scan register having a scan bit; a logic circuit coupled to the scan register and selectively decoding the scan bit; and a programmable delay circuit coupled to the logic circuit and delaying the signal a programmable amount of time in response to the decoded scan bit.
Claim 2
Dependent Claim
54 words
A circuit for delaying a signal comprising: a scan register having a scan bit; a logic circuit coupled to the scan register and selectively decoding the scan bit; and a programmable delay circuit coupled to the logic circuit and delaying the signal a programmable amount of time in response to the decoded scan bit.
Claim 3
Dependent Claim
12 words
The circuit of claim 1, wherein the signal is a clock signal.
Claim 4
Dependent Claim
26 words
The circuit of claim 1, wherein the scan register has a plurality of scan bits, and the logic circuit selectively decodes the plurality of scan bits.
Claim 5
Dependent Claim
34 words
The circuit of claim 3, wherein the programmable delay circuit comprises a plurality of delay paths, and wherein one of the delay paths is selected in response to the decoded plurality of scan bits.
Claim 6
Dependent Claim
53 words
The circuit of claim 3, wherein the programmable delay circuit comprises: a first plurality of delay circuits each having a different delay; and a second plurality of delay circuits each having a different delay, wherein the second plurality of delay circuits modify the delay of one of the first plurality of delay circuits.
Claim 7
Dependent Claim
46 words
The circuit of claim 1, wherein the programmable delay circuit comprises: a delay circuit configured to delay the signal; and a bypass circuit coupled to the delay circuit, wherein the bypass circuit is enabled in response to the decoded scan bit to bypass the delay circuit.
Claim 8
Dependent Claim
12 words
The circuit of claim 6, wherein the delay circuit comprises a resister.
Claim 9
Dependent Claim
12 words
The circuit of claim 6, wherein the delay circuit comprises a capacitor.
Claim 10
Dependent Claim
13 words
The circuit of claim 6, wherein the bypass circuit comprises a transmission gate.
Claim 11
Dependent Claim
71 words
The circuit of claim 6, wherein the logic circuit comprises: a programmable circuit generating a default signal; and a select circuit having a first input coupled to the default signal, a second input coupled to the scan bit, and a select input receiving a mode select signal, wherein the select circuit couples either the default signal or the scan bit to the bypass circuit in response to the mode select signal.
Claim 12
Dependent Claim
24 words
The circuit of claim 10, wherein the programmable circuit comprises a programmable element that can be programmed to enable or disable the bypass circuit.
Claim 13
Dependent Claim
12 words
The circuit of claim 11, wherein the programmable element is a fuse.
Claim 14
Dependent Claim
43 words
A memory device comprising: the circuit of claim 1; a memory array storing data; and a sense amplifier circuit coupled to the memory array and the circuit, wherein the signal enables the sense amplifier to sense the data stored in the memory array.
Claim 15
Dependent Claim
49 words
The circuit of claim 1, wherein the scan bit is loaded into the scan register in response to a scan enable input signal and a clock signal, and wherein the scan bit is output to the logic circuit from the scan register in response to a test mode signal.
Claim 16
Dependent Claim
33 words
A circuit for delaying a signal, comprising: means for storing a scan bit; means for selectively decoding the scan bit; and means for programmably delaying the signal in response to the decode means.
Claim 17
Dependent Claim
33 words
A circuit for delaying a signal, comprising: means for storing a scan bit; means for selectively decoding the scan bit; and means for programmably delaying the signal in response to the decode means.
Claim 18
Independent Claim
27 words
A method of delaying a signal, comprising: decoding a scan bit in a scan register; and programmably delaying the signal in response to decoding the scan bit.
Claim 19
Independent Claim
27 words
A method of delaying a signal, comprising: decoding a scan bit in a scan register; and programmably delaying the signal in response to decoding the scan bit.
Claim 20
Dependent Claim
22 words
The method of claim 16, wherein the delaying step comprises coupling the signal to one of a plurality of different delay paths.
Claim 21
Dependent Claim
24 words
The method of claim 16, wherein the delaying step comprises disabling a bypass circuit from a delay path that is coupled to the signal.
Claim 22
Independent Claim
56 words
A method of testing a device comprising the steps of: programming a scan bit into a scan register; decoding the scan bit; in response to the decoded scan bit, delaying a signal internal to the device for a predetermined period of time; and monitoring the operation of the device in response to delaying the internal signal.
Claim 23
Independent Claim
56 words
A method of testing a device comprising the steps of: programming a scan bit into a scan register; decoding the scan bit; in response to the decoded scan bit, delaying a signal internal to the device for a predetermined period of time; and monitoring the operation of the device in response to delaying the internal signal.
Claim 24
Dependent Claim
24 words
The method of claim 19, further comprising the step of programming a programmable element to a state corresponding to the predetermined period of time.
Claim 25
Dependent Claim
37 words
A circuit comprising: a first plurality of delay circuits each having a different delay; and a second plurality of delay circuits coupled to one of the first plurality of delay circuits and each having a different delay.
Claim 26
Dependent Claim
37 words
A circuit comprising: a first plurality of delay circuits each having a different delay; and a second plurality of delay circuits coupled to one of the first plurality of delay circuits and each having a different delay.
Claim 27
Dependent Claim
82 words
A circuit for delaying a signal comprising: a first delay circuit having an input coupled to the signal and an output; a second delay circuit having an input coupled to the signal and an output; a third delay circuit having an input coupled to the signal and an output; and a fourth delay circuit having an input coupled to each of the outputs of the second and third delay circuits, and an output coupled to the output of the first delay circuit.
Claim 28
Dependent Claim
82 words
A circuit for delaying a signal comprising: a first delay circuit having an input coupled to the signal and an output; a second delay circuit having an input coupled to the signal and an output; a third delay circuit having an input coupled to the signal and an output; and a fourth delay circuit having an input coupled to each of the outputs of the second and third delay circuits, and an output coupled to the output of the first delay circuit.
Claim 29
Dependent Claim
19 words
The circuit of claim 22, wherein each of the first, second, third, and fourth delay circuits have different delays.
Claim 30
Dependent Claim
22 words
The circuit of claim 22, wherein the first delay circuit is enabled to delay the signal in response to a control signal.
Claim 31
Dependent Claim
27 words
The circuit of claim 22, wherein the second delay circuit and the fourth delay circuit are enabled to delay the signal in response to a control signal.
Claim 32
Dependent Claim
27 words
The circuit of claim 22, wherein the third delay circuit and the fourth delay circuit are enabled to delay the signal in response to a control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |