US4951254A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static memory unit having a plurality of test modes, and computer equipped with such units
Assignee: US Philips Corp
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Filing: 1988-11-16
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Granted: 1990-08-21
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Expires: 2008-11-16
Abstract
Abstract Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.
Inventors
- 👤 Hans Ontrop
- 👤 Roelof Salters
- 👤 Betty Prince
- 👤 Thomas J. Davies
- 👤 Cathal G. Phelan
- 👤 Cormac O'Connell
- 👤 Peter H. Voss
- 👤 Leonardus C. M. G. Pfennings, deceased
- 👤 legal representative Henricus J. by Kunnen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:09
CPC Classifications
G; G11; G11C; G11C29/00; G06; G06F; G06F11/00; G06F11/22; G06F11/2273; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G06F11/006; G11C29/04; G11C29/08; G11C29/12; G11C29/46
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
153 words
A random access memory unit with direct access, comprising a parallel multi-bit address input and at least one data output, a write mode input for placing the unit in write mode, a unit selection input, and means for detecting whether a predefined sequence of logic signals, which violates specifications for said unit of a normal set of sequences which are used for said direct access so as to be normally prohibited, but the amplitudes of which are nevertheless included within a range of amplitudes specified for such signals, is supplied at said multi-bit address input and said write mode input, and for placing the unit in test mode when such predefined sequence has been detected wherein the predefined sequence comprises a modification of at least one of only the address data bits at said multi-bit address input while the unit has been placed in write mode, this constituting an aforesaid normally prohibited sequence.
Claim 2
Dependent Claim
153 words
A random access memory unit with direct access, comprising a parallel multi-bit address input and at least one data output, a write mode input for placing the unit in write mode, a unit selection input, and means for detecting whether a predefined sequence of logic signals, which violates specifications for said unit of a normal set of sequences which are used for said direct access so as to be normally prohibited, but the amplitudes of which are nevertheless included within a range of amplitudes specified for such signals, is supplied at said multi-bit address input and said write mode input, and for placing the unit in test mode when such predefined sequence has been detected wherein the predefined sequence comprises a modification of at least one of only the address data bits at said multi-bit address input while the unit has been placed in write mode, this constituting an aforesaid normally prohibited sequence.
Claim 3
Dependent Claim
42 words
The memory unit according to claim 1, characterized in that the means for placing the unit in test mode act only when the said predefined sequence of logic signals comprises two successive violations of the specifications of a normal set of sequences.
Claim 4
Dependent Claim
32 words
The memory unit according to claim 1, characterized in that the means for placing the unit in test mode act in consequence of the modification of only one of the address bits.
Claim 5
Dependent Claim
41 words
The memory unit according to any one of claims 1, 2, and 4 characterized in that it further comprises means for maintaining it in test mode while the unit selection and write mode inputs do not simultaneously receive a deactivation signal.
Claim 6
Dependent Claim
80 words
The memory unit according to any one of claims 1, 2, and 4, wherein said unit has a plurality of test modes and wherein said detecting and placing means is characterized in that input terminals for one or more bits of said multi-bit address input of the unit is connected to a test mode decoding circuit, in which the one or more bits are used as data defining the particular test mode into which the unit is to be placed.
Claim 7
Dependent Claim
93 words
The memory unit according to claim 1, further comprising a first buffer circuit for the output of the data contained within the memory cells, characterized in that it is further equipped with a second buffer circuit for the output of the data resulting from a test, which is activated in test mode, the outputs of both buffer circuits being connected to the data output of the unit, and, at least one buffer output of the two being in the high-impedance condition, in response to whether or not the unit is in test mode.
Claim 8
Dependent Claim
56 words
The memory unit according to any one of claim 1 which is equipped with a single data output pin, characterized in that said unit is equipped with means for serializing the data resulting from a test, the write mode input of the unit being connected to these means in order to serve them as clock input.
Claim 9
Dependent Claim
30 words
The memory unit according to claim 1 characterized in that it is equipped with means for supplying to a user, in test mode, information concerning the identification of the unit.
Claim 10
Dependent Claim
62 words
The memory unit according to claim 1 which is equipped with substitute circuits intended to be permanently used in place of normal circuits in the event of failure of one or more of the latter, characterized in that it is equipped with means for supplying to the user, in test mode, information concerning the use of or non-use of a substitute circuit.
Claim 11
Dependent Claim
65 words
The memory unit according to claim 1 which is equipped with an internal voltage generator operating from a supply input of the unit, intended to supply one or more subassemblies of the unit and producing, on an internal supply connection, a regulated voltage, characterized in that it is equipped with means for modifying the voltage applied to the said internal supply connection, in test mode.
Claim 12
Dependent Claim
29 words
The memory unit according to claim 10, characterized in that the said means establish a link between the said internal supply connection and the supply input of the unit.
Claim 13
Dependent Claim
23 words
The memory unit according to claim 1 characterized in that it is equipped with means for carrying out a self-check, in test mode.
Claim 14
Dependent Claim
88 words
The computer equipped with a plurality of memory units according to claim 12, characterized in that it is equipped with means for giving self-check commands successively to each one of the said memory units, in order then to determine a predefined time period, and in order, on the expiration of the said time period, to read successively the data presented at the output of each one of the memory units, in the same order, and with the same cyclic sequence as those used to give the self-check commands,.
Claim 15
Dependent Claim
32 words
The computer equipped with a plurality of memory units according to claim 1 characterized in that it is equipped with means for selectively addressing each unit and placing it in test mode.
Claim 16
Dependent Claim
19 words
The unit according to claim 1 characterized in that it is constructed in the form of an integrated circuit.
References Cited (Backward Citations)
US4811299A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |