US4843255A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-latching monostable circuit
Assignee: Tektronix Inc
•
Filing: 1988-02-10
•
Granted: 1989-06-27
•
Expires: 2008-02-10
Abstract
Abstract A monostable circuit responsive conditionally to a circuit input signal for generating a circuit output signal having a pulse of a predetermined duration includes an AND gate having two input ports and an output port. ONe of the input ports is coupled to the circuit input signal and inverts that signal. The other of the input ports is coupled to the circuit output signal. A reset OR gate receives a reset signal and the output of the AND gate. When the reset signal is low, the reset OR gate outputs the output of the AND gate, thus enabling the curcuit. The output of the reset OR gate also goes to a ramp generator having a ramp capacitor, the charging current to which is provided by a current driver. The reference voltage for a comparator is provided by circuitry identical to that associated with the ramp capacitor except that an intermediate bias reference is applied to it. This bias reference is compensated for the effect temperature changes on the circuit. An external current source operating through a current mirror drives the capacitor current driver and the reference voltage. The outputs of the comparator and the reset OR gate are input into the output OR gate for producing the circuit output signal. When the output signal is low, or logic true, the AND gate is latched so that changes in the circuit input signal during this time period do not affect circuit operation.
Inventors
- 👤 Carlton Stuebing
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:04
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K4/50; H03K3/00; H03K3/02; H03K3/023; H03K3/0232
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
273 words
A self-latching monostable circuit responsive conditionally to an input signal for generating an output signal having a pulse of a predetermined duration comprising: AND gate means having two input ports including an inverting input on one of the input ports and an output port, one of said input ports being coupled to the input signal and the other of said input ports being coupled to said output signal; OR gate means having two input ports for generating the output signal, one of said input ports of said OR gate means being coupled to said output of said AND gate means; and timing means having an input port coupled to said output port of said AND gate means, an output port coupled to the other of said input ports of said OR gate means, and a ramp capacitor coupled to the input port, the ramp capacitor being charged by a variable charging current, said timing means being responsive to the output of said AND gate means for changing the signal at said output port of said timing means from a first logic state to second logic state a predetermined period of time after the output of said AND gate means changes from a first logic state to a second logic state, said predetermined period of time being variable, whereby the output signal has a pulse of a predetermined width beginning when the input signal changes from a first to a second logic state while preventing further changes in the input signal from affecting the output signal during the predetermined duration, the output signal being latched in a predetermined logic state for the predetermined duration.
Claim 2
Dependent Claim
273 words
A self-latching monostable circuit responsive conditionally to an input signal for generating an output signal having a pulse of a predetermined duration comprising: AND gate means having two input ports including an inverting input on one of the input ports and an output port, one of said input ports being coupled to the input signal and the other of said input ports being coupled to said output signal; OR gate means having two input ports for generating the output signal, one of said input ports of said OR gate means being coupled to said output of said AND gate means; and timing means having an input port coupled to said output port of said AND gate means, an output port coupled to the other of said input ports of said OR gate means, and a ramp capacitor coupled to the input port, the ramp capacitor being charged by a variable charging current, said timing means being responsive to the output of said AND gate means for changing the signal at said output port of said timing means from a first logic state to second logic state a predetermined period of time after the output of said AND gate means changes from a first logic state to a second logic state, said predetermined period of time being variable, whereby the output signal has a pulse of a predetermined width beginning when the input signal changes from a first to a second logic state while preventing further changes in the input signal from affecting the output signal during the predetermined duration, the output signal being latched in a predetermined logic state for the predetermined duration.
Claim 3
Dependent Claim
102 words
A circuit according to claim 1 wherein said timing means further comprises timing ramp generating means for generating a timing signal having a voltage level varying at a predetermined rate in response to a change in logic level of the signal on the input to said timing means, means for comparing said timing signal and a reference voltage of generating a comparator signal having a pulse with a duration corresponding to the time said timing signal exceeds the reference voltage, and means for generating said reference voltage compensated for changes in the operation of said comparator means due to changes in temperature.
Claim 4
Dependent Claim
70 words
A circuit according to claim 2 wherein said means for generating said reference voltage further comprises transistor means and temperature compensating resistor means coupled in parallel to said transistor means for biasing said transistor means such that said resistor means varies in value according to changes in temperature of said resistors to compensate for changes in operation of said transistor means due to changes in temperature of said transistor means.
Claim 5
Dependent Claim
163 words
A circuit according to claim 1 wherein said timing means further comprises timing ramp generating means for generating a timing signal having a voltage level varying at a predetermined rate in response to a change in logic level of the signal on the input of said timing means, means for generating a reference voltage, means for comparing said timing signal and said reference voltage to generate a comparator signal having a pulse with a duration corresponding to the time said timing signal exceeds said reference voltage, and current mirror means having an input for receiving an externally applied current and first and second current outputs, said timing ramp generating means and reference voltage generating means each having a current input coupled to one of the first and second current outputs of said current mirror means in such a manner that any changes in bias of said timing ramp generating means are offset by corresponding changes in bias of said reference voltage generating means.
Claim 6
Dependent Claim
63 words
A circuit according to claim 1 further comprising a first voltage supply and wherein said timing means further comprises timing ramp capacitor means one side of which is tied directly to said first voltage supply, and emitter-follower transistor means coupled across said capacitor means, whereby voltage spikes generated by said emitter-follower transistor means are prevented from being transmitted to said first voltage supply.
Claim 7
Dependent Claim
30 words
A circuit according to claim 5 wherein said timing means further comprises current source means coupled to said capacitor means for generating a predetermined current for charging said capacitor means.
Claim 8
Dependent Claim
42 words
A circuit according to claim 6 wherein said timing means further comprises field-effect transistor means having a source coupled to said first voltage supply, the emitter of said emitter-follower transistor means being coupled directly to the gate of said field-effect transistor means.
Claim 9
Dependent Claim
23 words
A circuit according to claim 6 wherein said current source means is variable for varying the rate of charging of said capacitor means.
References Cited (Backward Citations)
US3210558A
Cited
US3192408A
Cited
US3346743A
Cited
US3353034A
Cited
US3484624A
Cited
US3588543A
Cited
US3892083A
Cited
US4293781A
Cited
US4509494A
Cited
US4667118A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-26 | 1992-12-26 | 1993-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-26 | 1996-12-26 | 1997-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-26 | 2000-12-26 | 2001-06-27 | $7700.00 | Window Closed / Lapsed |