← Back to Patent Explorer
US3353034A Expired / Lapsed US ⏱️ 0.0 years remaining

Pulse generator utilizing control signals to vary pulse width

Assignee: Individual
•
Filing: 1965-05-26
•
Granted: 1967-11-14
•
Expires: 1985-05-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

No abstract record available.

Inventors

  • 👤 Robert J Betz
  • 👤 George H Mcafee

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 22:15
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/284

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 184 words
IN A PULSE GENERATOR HAVING A TIME CONSTANT NETWORK FOR CONTROLLING THE WIDTH OF PULSES GENERATED THEREBY, SAID NETWORK CONSISTING OF A CAPACITOR AND RESISTIVE MEANS CONNECTED THERETO FOR PROVIDING A CHARGE PATH FOR SAID CAPACITOR; CONTROL MEANS COMPRISING: A PLURALITY OF IMPEDANCE NETWORKS CONNECTED IN PARALLEL WITH SAID RESISTIVE MEANS, EACH OF SAID IMPEDANCE NETWORKS CONSISTING OF A CONTROL RESISTOR AND A DIODE CONNECTED IN SERIES; AND A PLURALITY OF SWITCHING MEANS, ONE OF WHICH IS CONNECTED TO EACH OF SAID IMPEDANCE NETWORKS TO SWITCH THE CONDUCTION OF SAID DIODES BETWEEN STATES OF HIGH AND LOW IMPEDANCE SO THAT VARIOUS ONES OF SAID PLURALITY OF RESISTORS MAY BE SELECTIVELY CONNECTED IN PARALLLEL WITH SAID RESISTIVE MEANS, THEREBY CHANGING THE WIDTH OF SAID GENERATED PULSES, EACH OF SAID PLURALITY OF SWITCHING MEANS COMPRISING A TRANSISTOR HAVING INPUT AND OUTPUT ELECTRODES, SAID OUTPUT ELECTRODE BEING CONNECTED TO THE JUNCTION OF THE RESISTOR AND DIODE CONNECTION OF THE ONE OF SAID PLURALITY OF IMPEDANCE NETWORKS WHICH IS ASSOCIATED WITH SAID TRANSISTOR; AND A CONTROL INPUT TERMINAL CONNECTED TO THE INPUT ELECTRODE OF EACH OF SAID TRANSISTORS.
Claim 2
Dependent Claim 184 words
IN A PULSE GENERATOR HAVING A TIME CONSTANT NETWORK FOR CONTROLLING THE WIDTH OF PULSES GENERATED THEREBY, SAID NETWORK CONSISTING OF A CAPACITOR AND RESISTIVE MEANS CONNECTED THERETO FOR PROVIDING A CHARGE PATH FOR SAID CAPACITOR; CONTROL MEANS COMPRISING: A PLURALITY OF IMPEDANCE NETWORKS CONNECTED IN PARALLEL WITH SAID RESISTIVE MEANS, EACH OF SAID IMPEDANCE NETWORKS CONSISTING OF A CONTROL RESISTOR AND A DIODE CONNECTED IN SERIES; AND A PLURALITY OF SWITCHING MEANS, ONE OF WHICH IS CONNECTED TO EACH OF SAID IMPEDANCE NETWORKS TO SWITCH THE CONDUCTION OF SAID DIODES BETWEEN STATES OF HIGH AND LOW IMPEDANCE SO THAT VARIOUS ONES OF SAID PLURALITY OF RESISTORS MAY BE SELECTIVELY CONNECTED IN PARALLLEL WITH SAID RESISTIVE MEANS, THEREBY CHANGING THE WIDTH OF SAID GENERATED PULSES, EACH OF SAID PLURALITY OF SWITCHING MEANS COMPRISING A TRANSISTOR HAVING INPUT AND OUTPUT ELECTRODES, SAID OUTPUT ELECTRODE BEING CONNECTED TO THE JUNCTION OF THE RESISTOR AND DIODE CONNECTION OF THE ONE OF SAID PLURALITY OF IMPEDANCE NETWORKS WHICH IS ASSOCIATED WITH SAID TRANSISTOR; AND A CONTROL INPUT TERMINAL CONNECTED TO THE INPUT ELECTRODE OF EACH OF SAID TRANSISTORS.

References Cited (Backward Citations)

US3263223A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1970-11-13 1971-05-15 1971-11-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1974-11-13 1975-05-15 1975-11-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1978-11-13 1979-05-15 1979-11-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag