Circuit forming output pulse a selected delay after initiating pulse

Claim 2

A circuit for forming an output pulse (RAI) rising in response to the presence of a binary valued initiating pulse (RAS) and falling a predetermined time thereafter, comprising: a first node (Node1) and a second node (Node2) and means (T1, T4) for charging the first and second nodes in a predetermined polarity in the absence of the initiating pulse (RAS), an inverter circuit (INV9) having its input coupled to the second node and having its output connected to produce the output pulse (RAE) in response to the voltage at the second node, a third node and means (T2) interconnecting the first and second nodes for selectively discharging the second node through the first node and means (T2, T5, T7) responsive to the presence of the initiating pulse for discharging the first and second nodes, a third node (Node3) and a first delay segment (Inv1-Inv6) connected between the first node and the third node and providing a timing signal at the third node, and a second delay segment (Inv7-Inv8) having its input end coupled to the second node and forming a timing signal at its output end, the means (T2) interconnecting the first and second nodes being responsive to the timing signal at the third node (Node3) for isolating the second node from the first node before the fall of the output pulse, and means (T3) connected to respond to the signal at the output end of the second delay segment and connected to the input of the inverter circuit for charging the second node and thereby causing the inverting circuit to drop the output pulse.

Claim 3

The circuit for forming an output pulse of claim 1 wherein the means interconnecting the first and second nodes comprising an FET having its gate terminal connected to the third node, and its source terminal and its drain terminal connected between the first node and the second node respectively.

Claim 4

The circuit for forming an output pulse of claim 2 wherein the timing signal at the third node has the polarity of the node charging voltage.

Claim 5

The circuit for forming an output pulse of claim 2 wherein the means for charging the first node comprises an FET having its gate terminal connected to receive the initiating pulse.

Claim 6

The circuit for forming an output pulse of claim 3 wherein FET for charging the first node has its drain terminal connected to the first node.

Claim 7

The circuit for forming an output pulse of claim 3 wherein the circuit includes a power supply having power supply terminals and wherein the means for charging the second node includes an FET (T4) connected to conduct between the second node and a power supply terminal and having its gate connected to the circuit output to turn on in response to the absence of the output pulse.

Claim 8

The circuit for forming an output pulse of claim 6 wherein the means for connecting the output end of the second delay segment to the input of the inverter circuit comprises an FET (T3) having its gate terminal connected to the other end of the second delay segment and having its source and drain terminals connected between the power supply terminal and the second node respectively.

Claim 9

The circuit for forming an output pulse of claim 7 wherein the means for discharging the first and second nodes comprises two FETs connected in series circuit between the first node and ground for discharging the first node when both FETs are turned on, one FET (T7) being connected to turn on in response to a signal RSH defining in one binary state an operating mode requiring the rise of the output pulse substantially immediately after the initiating pulse and the other FET (T5) being connected to turn on in response to the initiating pulse.

Claim 10

The circuit for forming an output pulse of claim 8 wherein the means for discharging the first and second nodes further comprises a delay circuit (INV10-INV13) and a second series connection of two FETs, one FET (T8) being connected to turn on in response to the signal (RSH) defining an operating mode requiring the rise of the output pulse the predetermined delay after the initiating pulse, and the other FET (T6) being connected to turn on in response to the delayed signal, whereby the discharging of the first and second nodes and the consequent rise of the output pulse is delayed in response to the mode signifying signal.

Claim 11

The circuit for forming an output pulse of claim 9 wherein the first delay segment and the second delay segment each comprise a chain of inverter circuits.

Claim 12

A circuit for forming a memory addressing pulse (RAI) in a memory of the type that produces a binary valued signal RSH defining in one state a refresh operation requiring a predetermined delay between the rise of an initiating signal (RAS) and the rise of the memory addressing pulse and defining in the complement state a normal memory operation not requiring the delay, comprising: first and second terminals for connection to a power supply, a first node (Node1) and a second node (Node2) and means (T1, T4) for charging the first and second nodes respectively from the first power supply terminal in the absence of the initiating pulse (RAS), an inverter circuit (INV9) having its input coupled to the second node and having its output coupled to produce the memory addressing pulse (RAI) in response to the voltage at the second node, means (T2) interconnecting the first and second nodes for selectively discharging the second node through the first node and means (T2, T5, T7) coupled to the first node and responsive to the presence of the initiating pulse for discharging the first and second nodes to the second power supply terminal and thereby raising the memory addressing pulse, a third node (Node3) and a first delay segment (Inv1-Inv6) connected between the first node and the third node and providing a timing signal at the third node, and a second delay segment (Inv7-Inv8) having its input end connected to the second node and forming a timing signal at its output end, said means (T2) interconnecting the first and second nodes being responsive to the timing signal at the third node (Node3) for isolating the second node from the first node after the rise of the memory addressing pulse and preparatory for the fall of the memory address pulse, and means (T3) connected to respond to the signal at the output end of the second delay segment and connected to the input of the inverter circuit for charging the second node and thereby causing the inverting circuit to drop the memory addressing pulse.

Claim 13

A circuit for forming a memory addressing pulse (RAI) in a memory of the type that produces a binary valued signal RSH defining in one state a refresh operation requiring a predetermined delay between the rise of an initiating signal (RAS) and the rise of the memory addressing pulse and defining in the complement state a normal memory operation not requiring the delay, comprising: first and second terminals for connection to a power supply, a first node (Node1) and a second node (Node2) and means (T1, T4) for charging the first and second nodes respectively from the first power supply terminal in the absence of the initiating pulse (RAS), an inverter circuit (INV9) having its input coupled to the second node and having its output coupled to produce the memory addressing pulse (RAI) in response to the voltage at the second node, means (T2) interconnecting the first and second nodes for selectively discharging the second node through the first node and means (T2, T5, T7) coupled to the first node and responsive to the presence of the initiating pulse for discharging the first and second nodes to the second power supply terminal and thereby raising the memory addressing pulse, a third node (Node3) and a first delay segment (Inv1-Inv6) connected between the first node and the third node and providing a timing signal at the third node, and a second delay segment (Inv7-Inv8) having its input end connected to the second node and forming a timing signal at its output end, said means (T2) interconnecting the first and second nodes being responsive to the timing signal at the third node (Node3) for isolating the second node from the first node after the rise of the memory addressing pulse and preparatory for the fall of the memory address pulse, and means (T3) connected to respond to the signal at the output end of the second delay segment and connected to the input of the inverter circuit for charging the second node and thereby causing the inverting circuit to drop the memory addressing pulse.

Claim 14

The circuit for forming a memory addressing pulse of claim 11 wherein the means responsive to the timing signal at the third node comprises an FET (T2) having its gate terminal connected to the third node, its source terminal connected to the first node and its drain terminal connected to the second node respectively.

Claim 15

The circuit for forming a memory addressing pulse of claim 12 wherein the means for charging the second node includes an FET (T4) connected between the second node and a power supply terminal and having its gate connected to the circuit output to turn on in response to the absence of the memory addressing pulse.

Claim 16

The circuit for forming a memory addressing pulse of claim 13 wherein the means for discharging the first and second nodes comprises the series connection of two FETs, one FET (T7) being connected to turn on in response to a signal RSH defining in one binary state an operating mode requiring the rise of the memory addressing pulse substantially immediately after the initiating pulse and the other FET (T5) being connected to turn on in response to the initiating pulse and thereby discharge the nodes.

Claim 17

The circuit for forming a memory addressing pulse of claim 14 wherein the means for discharging the first and second nodes further comprises a delay circuit (Inv10-Inv13) and a second series connection of two FETs, one FET (T8) being connected to turn on in response to a signal (RSH) signifying an operating mode requiring the rise of the memory addressing pulse the predetermined delay after the initiating pulse, and the other FET (T6) being connected to turn on in response to the delayed signal at the output of the delay circuit, whereby the discharging of the first and second nodes and the consequent rise of the memory addressing pulse is delayed in response to the mode defining signal.