US4797573A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output circuit with improved timing control circuit
Assignee: NEC Electronics Corp
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Filing: 1987-01-29
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Granted: 1989-01-10
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Expires: 2007-01-29
Abstract
Abstract A memory output circuit which can ensure the sufficient width of output data even in the case of high speed memory operation. The output circuit comprises an output section, a driver circuit for controlling the output section in response to a control signal, and a delay circuit adapted to reset the driver circuit when a predetermined time has elapsed from the enabling of the output section.
Inventors
- 👤 Shoji Ishimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
286 words
A timing-controlled circuit comprising a first terminal for receiving a control signal; a second terminal for receiving a data signal; a control circuit having an enable terminal, a reset terminal and a control output terminal, each terminal assuming an active level or an inactive level, said control circuit making a level of said control output terminal active when a level of said enable terminal is active and a level of said reset terminal is inactive, and making said output terminal inactive when a level of said enable terminal is active and level of said reset terminal is active; a delay circuit having an input and an output and having a predetermined delay time; first means coupled to said first terminal and said enable terminal for making a level at said enable terminal active and inactive when said control signal is at a first level and at a second level, respectively; second means for connecting an input of said delay circuit to said control output terminal; third means for connecting an output of said delay circuit to said reset terminal thereby to make said reset terminal active after said predetermined delay time has elapsed from the time when said control output terminal is made active; a data section having an input terminal coupled to said second terminal for processing said data signal and a control terminal; and fourth means coupled to said control output terminal and said control terminal of said data section for enabling said data section only when said output control terminal is at the active level, whereby said data section processes said data signal only during said predetermined delay period from the time when said control output terminal is changed to the active level.
Claim 2
Dependent Claim
286 words
A timing-controlled circuit comprising a first terminal for receiving a control signal; a second terminal for receiving a data signal; a control circuit having an enable terminal, a reset terminal and a control output terminal, each terminal assuming an active level or an inactive level, said control circuit making a level of said control output terminal active when a level of said enable terminal is active and a level of said reset terminal is inactive, and making said output terminal inactive when a level of said enable terminal is active and level of said reset terminal is active; a delay circuit having an input and an output and having a predetermined delay time; first means coupled to said first terminal and said enable terminal for making a level at said enable terminal active and inactive when said control signal is at a first level and at a second level, respectively; second means for connecting an input of said delay circuit to said control output terminal; third means for connecting an output of said delay circuit to said reset terminal thereby to make said reset terminal active after said predetermined delay time has elapsed from the time when said control output terminal is made active; a data section having an input terminal coupled to said second terminal for processing said data signal and a control terminal; and fourth means coupled to said control output terminal and said control terminal of said data section for enabling said data section only when said output control terminal is at the active level, whereby said data section processes said data signal only during said predetermined delay period from the time when said control output terminal is changed to the active level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-10 | 1992-07-11 | 1993-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-10 | 1996-07-11 | 1997-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-10 | 2000-07-11 | 2001-01-10 | $7700.00 | Window Closed / Lapsed |