US5177375A
Expired / Lapsed
US
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Power on reset circuit for semiconductor integrated circuit device
Assignee: Mitsubishi Electric Corp
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Filing: 1990-12-14
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Granted: 1993-01-05
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Expires: 2010-12-14
Abstract
Abstract A semiconductor integrated circuit device comprising an internal reset circuit generating one shot pulse for resetting an internal circuit upon a power on. In the internal reset circuit, inputted to a two-input NOR gate are an output potential of an inverter inverting a first node coupled to a power supply through a capacitor, and an internal clock signal which level inverts at a predetermined timing after rising to a "H" level upon the power on. Then, the output of the NOR gate is applied to a second node in an internal circuit to be reset. The internal reset circuit outputs one shot pulses synchronizing with the first fall of the internal clock signal after the power on irrespective of a potential change rate of the first node after the power on. The first node is set to more easily attain a "H" level than the second node to be reset to a "L" level at the power on by adjusting characteristics of circuit elements connected to the first node and those of circuit elements connected to the second node. As a result, the second node is set to be without fail at a "L" level requiring no resetting when the inverted potential of the first node has a value allowing a generation of one shot pulses at the NOR gate, thereby preventing malfunction of the internal circuit due to erroneous resetting.
Inventors
- 👤 Toshiyuki Ogawa
- 👤 Shinji Kawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:31
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
201 words
A semiconductor integrated circuit device comprising internal clock signal generating means for generating an internal clock signal, internal circuit means operating in response to said internal clock signal and means for initializing said internal circuit means in response to a power supply potential applied from an external power supply and said internal clock signal, said initializing means including: a first node coupled to said power supply potential and being subjected to potential changes following the change in said power supply potential upon application of the external power supply, first circuit element means coupled to said first node for changing the potential at said first node reset signal generating means for generating a reset signal initializing said internal circuit means in response to a predetermined potential at said first node after application of the power supply potential from the external power supply, and to the internal clock signal, and means for delaying the reset signal for a predetermined time, wherein said first circuit element means is responsive to said delayed reset signal for changing the potential at said first node to ground potential, and said reset signal generating means includes a one-shot pulse generating means for generating a single pulse reset signal.
Claim 2
Dependent Claim
201 words
A semiconductor integrated circuit device comprising internal clock signal generating means for generating an internal clock signal, internal circuit means operating in response to said internal clock signal and means for initializing said internal circuit means in response to a power supply potential applied from an external power supply and said internal clock signal, said initializing means including: a first node coupled to said power supply potential and being subjected to potential changes following the change in said power supply potential upon application of the external power supply, first circuit element means coupled to said first node for changing the potential at said first node reset signal generating means for generating a reset signal initializing said internal circuit means in response to a predetermined potential at said first node after application of the power supply potential from the external power supply, and to the internal clock signal, and means for delaying the reset signal for a predetermined time, wherein said first circuit element means is responsive to said delayed reset signal for changing the potential at said first node to ground potential, and said reset signal generating means includes a one-shot pulse generating means for generating a single pulse reset signal.
Claim 3
Dependent Claim
146 words
The semiconductor integrated circuit device according to claim 1, wherein said internal circuit means comprises: function element means coupled to a second node and responsive to a potential at said second node which changes, means coupled to said second node and responsive to said reset signal for supplying a potential to said second node for initializing said internal circuit means, and second circuit element means coupled to said second node for holding the potential at said second node, wherein an amount of potential change at said first node changed by said first circuit element means and an amount of potential change of said second node are different from each other and said second node attains a potential required for initializing said internal circuit means when said reset signal generating means generates no reset signal after application of the power supply potential from the external power supply.
Claim 4
Dependent Claim
47 words
The semiconductor integrated circuit device according to claim 1, wherein said one-shot pulse generating means is responsive to said internal clock signal for providing said single pulse reset signal synchronizing with a first level inversion of said internal clock signal after application of the external power supply.
Claim 5
Dependent Claim
67 words
The semiconductor integrated circuit device according to claim 2, further including a first coupling capacitance means coupled between said first node and said power supply potential, wherein said second circuit element means includes a second coupling capacitance means coupled between said second node and ground, said predetermined potential comprises said power supply potential, and said potential required for initializing said function element means comprises said ground potential.
Claim 6
Dependent Claim
110 words
The semiconductor integrated circuit device according to claim 2, wherein said reset signal generating means includes a first field effect semiconductor element coupling said first node to said power supply potential and a second field effect semiconductor element coupling said first node to the ground potential, and said function element means includes a third field effect semiconductor element coupling said second node to said power supply potential and a fourth field effect semiconductor element coupling said second node to the ground potential, wherein threshold voltage and channel length of said first and second field effect semiconductor elements are different from those of said third and fourth field effect semiconductor elements.
Claim 7
Dependent Claim
53 words
The semiconductor integrated circuit device according to claim 3, wherein said function element means includes first inverting means for inverting the potential of said second node and second inverting means for inverting an output potential of said first inverting means, an output of said second inverting means is applied to said second node.
Claim 8
Dependent Claim
67 words
The semiconductor integrated circuit device according to claim 2, wherein said function element means includes means for inverting the potential of said second node, fuse means for coupling said second node to said power supply potential and a field effect semiconductor element for coupling said second node to the ground potential, said field effect semiconductor element has a control terminal receiving the output of said inverting means.
Claim 9
Dependent Claim
53 words
The semiconductor integrated circuit device according to claim 2, wherein said means for supplying a potential includes a field effect semiconductor element comprising a first conduction terminal connected to said second node, a second conduction terminal receiving said ground potential and a control terminal receiving an output of said reset signal generating means.
Claim 10
Dependent Claim
108 words
The semiconductor integrated circuit device according to claim 3, wherein said one shot pulse generating means includes: first inverting means for inverting the potential at said first node, means for maintaining the potential at said first node in response to an output of said first inverting means, and logic gate means receiving as inputs the output of said first inverting means and said internal clock signal, and providing an output in response thereto, wherein said first circuit element means is responsive to the delayed reset signal to invert the potential at said first node in response to a potential level of said output of said logic gate means.
Claim 11
Dependent Claim
108 words
The semiconductor integrated circuit device according to claim 6, wherein said reset signal generating means comprises: third inverting means for inverting the potential at said first node, fourth inverting means for inverting the output of said first inverting means and applying the output to said first node, and logic gate means receiving as inputs the outputs of said third inverting means and said internal clock means, and providing an output in response thereto, wherein said first circuit element means is responsive to the delayed reset signal to invert the potential at said first node in response to a potential level of said output of said logic gate means.
Claim 12
Dependent Claim
119 words
The semiconductor integrated circuit device according to claim 7, wherein said reset signal generating means comprises: third inverting means for inverting the potential at said first node, a field effect semiconductor element for coupling said first node to said ground potential, said field effect semiconductor element having a control terminal receiving the output of said third inverting means, and logic gate means receiving as inputs the outputs of said third inverting means and said internal clock signal, and outputting potential levels in response thereto, wherein said first circuit element means is responsive to the delayed reset signal to invert the potential at said first node in response to a potential level of said output of said logic gate means.
Claim 13
Dependent Claim
19 words
The semiconductor integrated circuit device according to claim 9, wherein said logic gate means includes a two-input NOR gate.
Claim 14
Dependent Claim
136 words
A semiconductor integrated circuit device for initializing a circuit operating in response to a clock signal, comprising: a node, raising means responsive to application of an external power supply for raising the potential of said node to a power supply potential, means for inverting the potential of said node raised by said raising means and for holding the inverted potential, logic gate means receiving as inputs the output of said inverting and holding means (25, and said clock signal, the output of said logic gate means being applied to said circuit as a reset signal for initializing said circuit, means for delaying by a predetermined time the output of said logic gate means, and means responsive to the delayed output of said means for delaying for lowering the potential at said node to a ground potential.
Claim 15
Dependent Claim
136 words
A semiconductor integrated circuit device for initializing a circuit operating in response to a clock signal, comprising: a node, raising means responsive to application of an external power supply for raising the potential of said node to a power supply potential, means for inverting the potential of said node raised by said raising means and for holding the inverted potential, logic gate means receiving as inputs the output of said inverting and holding means (25, and said clock signal, the output of said logic gate means being applied to said circuit as a reset signal for initializing said circuit, means for delaying by a predetermined time the output of said logic gate means, and means responsive to the delayed output of said means for delaying for lowering the potential at said node to a ground potential.
Claim 16
Dependent Claim
19 words
The semiconductor integrated circuit device according to claim 13, wherein said logic gate means includes a two-input NOR gate.
References Cited (Backward Citations)
US4140930A
Cited
EP0150480A2
Cited
DE3515611A1
Cited
US4788454A
Cited
US4716302A
Cited
US4886984A
Cited
US4933902A
Cited
EP0303257A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-05 | 1996-07-06 | 1997-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-05 | 2000-07-06 | 2001-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-05 | 2004-07-06 | 2005-01-05 | $7700.00 | Window Closed / Lapsed |