US4933902A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of and apparatus for reducing current of semiconductor memory device
Assignee: Mitsubishi Electric Corp
•
Filing: 1988-07-22
•
Granted: 1990-06-12
•
Expires: 2008-07-22
Abstract
Abstract A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level row address strobe (RAS) signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic random access memory (RAM) at the time of turning on the power supply.
Inventors
- 👤 Michihiro Yamada
- 👤 Hiroshi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
191 words
A semiconductor memory device operative in a first operating state and a second operating state, wherein said memory device consumes more current in said first operating state than in said second operating state, said semiconductor memory device comprising: at least one memory cell for storing data; first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states; detector means for detecting an application of power to said memory device; reset pulse generating means responsive to said detector means for generating a power on reset pulse signal defining said second operating state of said memory device, said power on reset pulse signal generating means including; (a) a power supply, (b) a series connection of a resistance means and capacitance means connected between said power supply and a ground potential, and (c) an inverter means having an input connected to a node where said resistance means and said capacitance means are connected together; and second control means responsive to the external control signal or said power on reset pulse signal for operating said memory device in said second operating state,
Claim 2
Dependent Claim
191 words
A semiconductor memory device operative in a first operating state and a second operating state, wherein said memory device consumes more current in said first operating state than in said second operating state, said semiconductor memory device comprising: at least one memory cell for storing data; first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states; detector means for detecting an application of power to said memory device; reset pulse generating means responsive to said detector means for generating a power on reset pulse signal defining said second operating state of said memory device, said power on reset pulse signal generating means including; (a) a power supply, (b) a series connection of a resistance means and capacitance means connected between said power supply and a ground potential, and (c) an inverter means having an input connected to a node where said resistance means and said capacitance means are connected together; and second control means responsive to the external control signal or said power on reset pulse signal for operating said memory device in said second operating state,
Claim 3
Dependent Claim
188 words
A semiconductor memory device having a memory cell for storing data, said memory device receiving an external row address strobe signal and being operative selectively in first and second operating states, wherein said memory device consumes more current in said first operating state than in said second operating state, said semiconductor memory device comprising: a reset signal generator circuit having an FET and a capacitor coupled in series with each other between a first potential source and a second potential source, and an inverter circuit having an input terminal coupled to a node between said FET and said capacitor and an output terminal for providing a control signal; and a NOR logic circuit having first and second input terminals and an output terminal, said first input terminal receiving said external row address strobe signal, said second input terminal coupled to said output terminal of said inverter circuit to receive said control signal, and said output terminal of said NOR logic circuit providing an internal row address strobe signal for controlling said memory device to operate selectively in one or the other of said first and second operating states.
Claim 4
Dependent Claim
188 words
A semiconductor memory device having a memory cell for storing data, said memory device receiving an external row address strobe signal and being operative selectively in first and second operating states, wherein said memory device consumes more current in said first operating state than in said second operating state, said semiconductor memory device comprising: a reset signal generator circuit having an FET and a capacitor coupled in series with each other between a first potential source and a second potential source, and an inverter circuit having an input terminal coupled to a node between said FET and said capacitor and an output terminal for providing a control signal; and a NOR logic circuit having first and second input terminals and an output terminal, said first input terminal receiving said external row address strobe signal, said second input terminal coupled to said output terminal of said inverter circuit to receive said control signal, and said output terminal of said NOR logic circuit providing an internal row address strobe signal for controlling said memory device to operate selectively in one or the other of said first and second operating states.
References Cited (Backward Citations)
US3562555A
Cited
US4216389A
Cited
US4451742A
Cited
US4409501A
Cited
US4654829A
Cited
US4712196A
Cited
US4788454A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |