US4451742A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power supply control for integrated circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1981-05-27
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Granted: 1984-05-29
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Expires: 2001-05-27
Abstract
Abstract A power supply control circuit (20) selectively provides power to an integrated circuit from either a primary power supply terminal (22), or through terminals (24, 26) connected to backup batteries. The voltage level of the primary power is monitored continuously and when it drops to a predetermined level one of the two backup batteries is substituted to power the integrated circuit in a power-down mode. The circuit (20) includes a level detector circuit (32) and a voltage reference circuit (98). In the power-down mode one battery is connected to power the integrated circuit and this battery is continuously monitored. When the voltage of the on-line battery drops to below a fixed level in comparison to off-line battery a control logic circuit (92) activates switches (56) to substitute the off-line battery for the on-line battery. Control logic circuitry (92) is provided to disconnect the control signals from the integrated circuit to prevent loss of stored information. Further the failure of one of the backup batteries is indicated by disabling a write enable signal.
Inventors
- 👤 Cecil J. Aswell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:59
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/28; G11; G11C; G11C5/00; G11C5/14; G11C5/141; Y; Y10; Y10S; Y10S331/00; Y10S331/03
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
112 words
A method for providing power to an integrated circuit from one of a plurality of sources, comprising the steps of: providing a primary power source and first and second backup power sources; comparing the voltages of said first and said second backup power sources to select the backup power source having the higher voltage; connecting the one of said backup power sources having the higher voltage to supply power to said integrated circuit when the voltage of said primary power source is less than a first predetermined voltage; and disabling input signals to said integrated circuit when the voltage of the power source connected thereto is less than a second predetermined voltage.
Claim 2
Independent Claim
112 words
A method for providing power to an integrated circuit from one of a plurality of sources, comprising the steps of: providing a primary power source and first and second backup power sources; comparing the voltages of said first and said second backup power sources to select the backup power source having the higher voltage; connecting the one of said backup power sources having the higher voltage to supply power to said integrated circuit when the voltage of said primary power source is less than a first predetermined voltage; and disabling input signals to said integrated circuit when the voltage of the power source connected thereto is less than a second predetermined voltage.
Claim 3
Dependent Claim
32 words
The method recited in claim 1 including the step of disabling input signals to said integrated circuit when the voltage of the power source connected thereto is less than a predetermined voltage.
Claim 4
Dependent Claim
74 words
The method recited in claim 1 including the steps of: monitoring the voltages of said batteries, and disabling a write enable input signal to said memory when said memory is powered by said primary power source and the voltage of one of said batteries is less than a third predetermined voltage, the disabling of said write enable input signal preventing the writing of data in said memory and serving as a battery failure warning.
Claim 5
Dependent Claim
33 words
The method recited in claim 3 wherein said first predetermined voltage is selected to be less than said second predetermined voltage and also is selected to be greater than said third predetermined voltage.
Claim 6
Independent Claim
171 words
A method for providing power to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip select signal to permit reading of data states in said memory, comprising the steps of: providing a primary power source and at least one backup power source; connecting said primary power source to power said memory when the voltage of said primary power source exceeds essentially the voltage of said backup power source; connecting said backup power source to power said memory when the voltage of said primary power source is less than a first preselected voltage; disabling said write enable signal provided to said memory when said primary power source is connected to power said memory and the voltage of said backup power source is less than a second preselected voltage; and disabling said write enable signal and said chip select signal provided to said memory when the voltage of said primary power source is less than a third preselected voltage.
Claim 7
Independent Claim
171 words
A method for providing power to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip select signal to permit reading of data states in said memory, comprising the steps of: providing a primary power source and at least one backup power source; connecting said primary power source to power said memory when the voltage of said primary power source exceeds essentially the voltage of said backup power source; connecting said backup power source to power said memory when the voltage of said primary power source is less than a first preselected voltage; disabling said write enable signal provided to said memory when said primary power source is connected to power said memory and the voltage of said backup power source is less than a second preselected voltage; and disabling said write enable signal and said chip select signal provided to said memory when the voltage of said primary power source is less than a third preselected voltage.
Claim 8
Dependent Claim
182 words
A power control circuit for connecting one of a plurality of power sources to an integrated circuit, comprising; a first power terminal for receiving a primary power source; a second power terminal for receiving a first backup power source; a third power terminal for receiving a second backup power source; means for comparing the voltages of said second and said third power terminals and connecting the power terminal having the higher voltage to a power terminal of said integrated circuit when the voltage at said first power terminal is less than a first predetermined voltage; and means for connecting said first power terminal to said integrated circuit power terminal when the voltage at said first power terminal exceeds by a preset threshold the voltage at said integrated circuit power terminal; means for comparing the voltage at said first power terminal to a second predetermined voltage for producing a control signal; and means responsive to said control signal for disabling the input command signals to said integrated circuit when the voltage at said first power terminal is less than said second predetermined voltage.
Claim 9
Dependent Claim
182 words
A power control circuit for connecting one of a plurality of power sources to an integrated circuit, comprising; a first power terminal for receiving a primary power source; a second power terminal for receiving a first backup power source; a third power terminal for receiving a second backup power source; means for comparing the voltages of said second and said third power terminals and connecting the power terminal having the higher voltage to a power terminal of said integrated circuit when the voltage at said first power terminal is less than a first predetermined voltage; and means for connecting said first power terminal to said integrated circuit power terminal when the voltage at said first power terminal exceeds by a preset threshold the voltage at said integrated circuit power terminal; means for comparing the voltage at said first power terminal to a second predetermined voltage for producing a control signal; and means responsive to said control signal for disabling the input command signals to said integrated circuit when the voltage at said first power terminal is less than said second predetermined voltage.
Claim 10
Dependent Claim
20 words
The power control circuit recited in claim 6 wherein said first predetermined voltage is less than said second predetermined voltage.
Claim 11
Dependent Claim
244 words
A power control circuit for connecting one of a plurality of power sources to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading and writing of data states in said memory, comprising: a first power terminal for receiving a primary power source; a second power terminal for receiving a first backup power source; a third power terminal for receiving a second backup power source; means for comparing the voltages at said second and said third power terminals to select the one of the two terminals having the higher voltage and for connecting the higher voltage terminal supply to said memory when the voltage at said first power terminal is below a first preselected voltage; means for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds by a preset threshold the voltage of the higher voltage terminal of said second and third terminals; means connected to said second and said third power terminals for disabling said write enable signal provided to said memory when the voltage at said second or said third power terminal is less than a second preselected voltage and; means connected to said first power terminal for disabling said write enable and said chip select signals provided to said memory when the voltage at said first power terminal is less than a third preselected voltage.
Claim 12
Dependent Claim
244 words
A power control circuit for connecting one of a plurality of power sources to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading and writing of data states in said memory, comprising: a first power terminal for receiving a primary power source; a second power terminal for receiving a first backup power source; a third power terminal for receiving a second backup power source; means for comparing the voltages at said second and said third power terminals to select the one of the two terminals having the higher voltage and for connecting the higher voltage terminal supply to said memory when the voltage at said first power terminal is below a first preselected voltage; means for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds by a preset threshold the voltage of the higher voltage terminal of said second and third terminals; means connected to said second and said third power terminals for disabling said write enable signal provided to said memory when the voltage at said second or said third power terminal is less than a second preselected voltage and; means connected to said first power terminal for disabling said write enable and said chip select signals provided to said memory when the voltage at said first power terminal is less than a third preselected voltage.
Claim 13
Dependent Claim
29 words
The power control circuit recited in claim 8 wherein said first preselected voltage is less than said second predetermined voltage and also is greater than said third predetermined voltage.
Claim 14
Dependent Claim
357 words
A power control circuit for connecting one of a plurality of power sources to an integrated circuit which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading of data states in said memory comprising circuit elements fabricated integrally with said memory, said power control circuit comprising: a first power terminal for receiving a primary power source; a second power terminal for receiving a first backup power source; a third power terminal for receiving a second backup power source; means for comparing the voltage at said first power terminal to the voltages at said second and said third power terminals for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds the voltages at said first or second power terminals; means for comparing the voltages at said second and said third power terminals for selecting one of the terminals having the higher voltage and connecting the higher voltage terminal to said memory when the voltage at said first power terminal is less than that of said higher voltage terminal; a voltage divider network connected between said first power terminal and ground and having a reference node; a band gap reference circuit for comparing a reference voltage with the input thereto; means for periodically connecting the input of said band gap reference circuit to the junction node of said voltage divider network, said second power terminal and said third power terminal; means connected to said band gap reference circuit for disabling said write enable and said chip enable signals provided to said memory when the voltage at said first power terminal is less than a predetermined voltage; and means connected to said band gap reference circuit for disabling said write enable signal when the voltage at said first power terminal is greater than said reference voltage and the voltage at either said second or said third power terminals in less than a preselected voltage that indicates a defective backup power source, the disabling of said write enable signal indicating that one of said backup power sources is defective.
Claim 15
Dependent Claim
357 words
A power control circuit for connecting one of a plurality of power sources to an integrated circuit which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading of data states in said memory comprising circuit elements fabricated integrally with said memory, said power control circuit comprising: a first power terminal for receiving a primary power source; a second power terminal for receiving a first backup power source; a third power terminal for receiving a second backup power source; means for comparing the voltage at said first power terminal to the voltages at said second and said third power terminals for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds the voltages at said first or second power terminals; means for comparing the voltages at said second and said third power terminals for selecting one of the terminals having the higher voltage and connecting the higher voltage terminal to said memory when the voltage at said first power terminal is less than that of said higher voltage terminal; a voltage divider network connected between said first power terminal and ground and having a reference node; a band gap reference circuit for comparing a reference voltage with the input thereto; means for periodically connecting the input of said band gap reference circuit to the junction node of said voltage divider network, said second power terminal and said third power terminal; means connected to said band gap reference circuit for disabling said write enable and said chip enable signals provided to said memory when the voltage at said first power terminal is less than a predetermined voltage; and means connected to said band gap reference circuit for disabling said write enable signal when the voltage at said first power terminal is greater than said reference voltage and the voltage at either said second or said third power terminals in less than a preselected voltage that indicates a defective backup power source, the disabling of said write enable signal indicating that one of said backup power sources is defective.
Claim 16
Independent Claim
126 words
A method of operation for an integrated circuit which is powered by either a primary power source or a backup power source, wherein operation of the integrated circuit is directed by at least one control signal input thereto, comprising the steps of: connecting said primary power source to power said integrated circuit when the voltage of said primary power source exceeds a first predetermined voltage, connecting said backup power source to power said integrated circuit when the voltage of said primary power source is less than said first predetermined voltage, and disabling said control signal to at least partially suspend operation of said integrated circuit when the voltage of said primary power source is less than a second predetermined voltage different from said first predetermined voltage.
Claim 17
Independent Claim
126 words
A method of operation for an integrated circuit which is powered by either a primary power source or a backup power source, wherein operation of the integrated circuit is directed by at least one control signal input thereto, comprising the steps of: connecting said primary power source to power said integrated circuit when the voltage of said primary power source exceeds a first predetermined voltage, connecting said backup power source to power said integrated circuit when the voltage of said primary power source is less than said first predetermined voltage, and disabling said control signal to at least partially suspend operation of said integrated circuit when the voltage of said primary power source is less than a second predetermined voltage different from said first predetermined voltage.
Claim 18
Independent Claim
122 words
A method of operation for an integrated circuit, which is powered by either a primary power source or a backup power source, wherein the operation of the integrated circuit is directed by at least one control signal input thereto, comprising the steps of: monitoring the voltage of said backup power source, while said integrated circuit is powered by said primary power source, for detecting a failure of said backup power source when the voltage of said backup power source becomes less than a predetermined voltage, and disabling said control signal upon detection of the failure of said backup power source for at least partially suspending the operation of said integrated circuit while said integrated circuit is powered by said primary power source.
Claim 19
Independent Claim
122 words
A method of operation for an integrated circuit, which is powered by either a primary power source or a backup power source, wherein the operation of the integrated circuit is directed by at least one control signal input thereto, comprising the steps of: monitoring the voltage of said backup power source, while said integrated circuit is powered by said primary power source, for detecting a failure of said backup power source when the voltage of said backup power source becomes less than a predetermined voltage, and disabling said control signal upon detection of the failure of said backup power source for at least partially suspending the operation of said integrated circuit while said integrated circuit is powered by said primary power source.
Claim 20
Dependent Claim
32 words
A method as recited in claim 12 wherein said step of monitoring comprises periodically comparing the voltage of said backup power supply to a reference voltage which serves as said predetermined voltage.
Claim 21
Dependent Claim
35 words
A method as recited in claim 12 wherein said step of disabling said control signal comprises inputting said control signal and a disable signal to a NAND gate which produces a selectively disabled control signal.
Claim 22
Independent Claim
111 words
A method of operation for an integrated circuit memory which is powered by either a primary power source or a backup battery, wherein the write function of the memory is controlled by a write enable signal input thereto, comprising the steps of: monitoring the voltage of said battery, while said memory is powered by said primary power source, for detecting a failure of said battery when the voltage of said battery becomes less than a predetermined voltage, and disabling said write enable signal upon detection of the failure of said battery for suspending the writing of the data into said memory while said memory is owered by said primary power source.
Claim 23
Independent Claim
111 words
A method of operation for an integrated circuit memory which is powered by either a primary power source or a backup battery, wherein the write function of the memory is controlled by a write enable signal input thereto, comprising the steps of: monitoring the voltage of said battery, while said memory is powered by said primary power source, for detecting a failure of said battery when the voltage of said battery becomes less than a predetermined voltage, and disabling said write enable signal upon detection of the failure of said battery for suspending the writing of the data into said memory while said memory is owered by said primary power source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-29 | 1987-11-28 | 1988-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-29 | 1991-11-28 | 1992-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-29 | 1995-11-28 | 1996-05-29 | $7700.00 | Window Closed / Lapsed |