US3562555A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory protecting circuit
Assignee: RCA Corp
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Filing: 1967-09-01
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Granted: 1971-02-09
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Expires: 1987-09-01
Abstract
Abstract A circuit for monitoring the power supply for a memory system which is arranged to inhibit operation of the memory system during a power supply failure while maintaining a temporary supply of power to the memory system.
Inventors
- 👤 Richard W Ahrons
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:22
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G06; G06F; G06F11/00; G06F11/002; G06F11/07; G06F11/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
132 words
A circuit comprising a transistor having a base, emitter and collector, an input terminal arranged to be connected to a power supply, first circuit means connecting said emitter to said terminal, a first output terminal, second circuit means connecting said vase to said output terminal, a second output terminal, third circuit means connecting said collector to said second terminal, a resistor connected between said collector and a point of reference potential, and a source of emergency power connected to said first output terminal and operative upon a fault of said power supply to reverse bias the emitter-base junction of said transistor while supplying power to said first output terminal, said source comprising a battery and a diode connected in series with the battery and poled to allow current flow from said battery.
Claim 2
Dependent Claim
132 words
A circuit comprising a transistor having a base, emitter and collector, an input terminal arranged to be connected to a power supply, first circuit means connecting said emitter to said terminal, a first output terminal, second circuit means connecting said vase to said output terminal, a second output terminal, third circuit means connecting said collector to said second terminal, a resistor connected between said collector and a point of reference potential, and a source of emergency power connected to said first output terminal and operative upon a fault of said power supply to reverse bias the emitter-base junction of said transistor while supplying power to said first output terminal, said source comprising a battery and a diode connected in series with the battery and poled to allow current flow from said battery.
Claim 3
Dependent Claim
125 words
A combination cOmprising a transistor having a base, emitter and collector, an input terminal arranged to be connected to a power supply, first circuit means connecting said emitter to said terminal, a first output terminal, second circuit means connecting said base to said first output terminal, a volatile memory system, means connecting said output terminal to said memory to supply power thereto, a second output terminal, third circuit means connecting said collector to said second terminal, a resistor connected between said collector and a point of reference potential, a signal-gating means operative to control the operation of said memory and fourth circuit means connecting said second output terminal to said gating means to apply a control signal thereto derived from a voltage across said resistor.
Claim 4
Dependent Claim
125 words
A combination cOmprising a transistor having a base, emitter and collector, an input terminal arranged to be connected to a power supply, first circuit means connecting said emitter to said terminal, a first output terminal, second circuit means connecting said base to said first output terminal, a volatile memory system, means connecting said output terminal to said memory to supply power thereto, a second output terminal, third circuit means connecting said collector to said second terminal, a resistor connected between said collector and a point of reference potential, a signal-gating means operative to control the operation of said memory and fourth circuit means connecting said second output terminal to said gating means to apply a control signal thereto derived from a voltage across said resistor.
Claim 5
Dependent Claim
39 words
A combination as set forth in claim 2 and including a source of emergency power connected to said first output terminal which source is operative upon a fault of said power supply to supply power to said memory system.
Claim 6
Dependent Claim
14 words
A combination as set forth in claim 3 wherein said source is a capacitor.
Claim 7
Dependent Claim
117 words
A combination comprising memory means, a first power supply means for said memory means, switching means arranged to normally connect said first power supply means to said memory means, a second power supply means for said memory means, means responsive to a proper operation of said first power supply and operative upon an improper operation thereof to operate said switching means to disconnect said first power supply means from said memory means and to supply power to said memory means, memory-addressing means for addressing said memory means, and inhibit means responsive to a disconnect operation of said switching means by said second power supply means to inhibit said memory-addressing means to prevent further addressing of said memory.
Claim 8
Dependent Claim
117 words
A combination comprising memory means, a first power supply means for said memory means, switching means arranged to normally connect said first power supply means to said memory means, a second power supply means for said memory means, means responsive to a proper operation of said first power supply and operative upon an improper operation thereof to operate said switching means to disconnect said first power supply means from said memory means and to supply power to said memory means, memory-addressing means for addressing said memory means, and inhibit means responsive to a disconnect operation of said switching means by said second power supply means to inhibit said memory-addressing means to prevent further addressing of said memory.
Claim 9
Dependent Claim
33 words
The combination as set forth in claim 5 wherein said switching means includes a transistor having a base-emitter junction providing a current path between said memory means and said first power supply means.
Claim 10
Dependent Claim
32 words
The combination as set forth in claim 6 wherein said second power supply means includes a capacitor arranged to back-bias said emitter-base junction upon the failure of said first power supply means.
Claim 11
Dependent Claim
43 words
The combination as set forth in claim 6 wherein said switching means includes a resistor connected between a collector of said transistor and a point of reference potential and said inhibit means includes gating means responsive to a signal developed across said resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-08 | 1974-08-10 | 1975-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-08 | 1978-08-10 | 1979-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-08 | 1982-08-10 | 1983-02-09 | $7700.00 | Window Closed / Lapsed |