Trench transistor with localized source/drain regions implanted through selectively grown oxide layer

Claim 1

A method of forming an IGFET, the method comprising the steps of: forming a trench with opposing sidewalls and a bottom surface in a substrate; selectively growing an oxide layer on the bottom surface so that the oxide layer includes a thick region between thin regions; implanting localized source and drain regions through the thin regions using the thick region as an implant mask; forming a gate electrode in the trench; and forming a source and a drain in the substrate, wherein the source includes the localized source region adjacent to the bottom surface of the trench and the drain includes the localized drain region adjacent to the bottom surface of the trench.

Claim 2

A method of forming an IGFET, the method comprising the steps of: forming a trench with opposing sidewalls and a bottom surface in a substrate; selectively growing an oxide layer on the bottom surface so that the oxide layer includes a thick region between thin regions; implanting localized source and drain regions through the thin regions using the thick region as an implant mask; forming a gate electrode in the trench; and forming a source and a drain in the substrate, wherein the source includes the localized source region adjacent to the bottom surface of the trench and the drain includes the localized drain region adjacent to the bottom surface of the trench.

Claim 15

A method of forming an IGFET, the method comprising the steps of: forming a trench partially through a substrate, wherein the trench includes opposing first and second sidewalls and a bottom surface; forming an oxide layer on the bottom surface; forming first spacers in the trench over outer portions of the oxide layer on the bottom surface, wherein a central portion of the oxide layer on the bottom surface between the first spacers is exposed; selectively growing the oxide layer by applying thermal oxidation after forming the first spacers, so that the central portion of the oxide layer is thicker than the outer portions of the oxide layer, and the oxide layer includes a thick region between thin regions on the bottom surface; removing the first spacers after selectively growing the oxide layer; implanting localized source and drain regions through the thin regions into the substrate using the thick region as an implant mask after removing the first spacers; removing the oxide layer after implanting the localized source and drain regions; forming a gate insulator on the bottom surface and second spacers on the sidewalls after removing the oxide layer; forming a gate electrode on the gate insulator and the second spacers, wherein the gate electrode is in the trench and spaced from and electrically isolated from the substrate; implanting sidewall source and drain regions through a top surface of the substrate; and forming a source and a drain in the substrate, wherein the source includes the localized source region adjacent to the bottom surface of the trench and the sidewall source region adjacent to the first sidewall, and the drain includes the localized drain region adjacent to the bottom surface of the trench and the sidewall drain region adjacent to the second sidewall.

Claim 16

A method of forming an IGFET, the method comprising the steps of: forming a trench partially through a substrate, wherein the trench includes opposing first and second sidewalls and a bottom surface; forming an oxide layer on the bottom surface; forming first spacers in the trench over outer portions of the oxide layer on the bottom surface, wherein a central portion of the oxide layer on the bottom surface between the first spacers is exposed; selectively growing the oxide layer by applying thermal oxidation after forming the first spacers, so that the central portion of the oxide layer is thicker than the outer portions of the oxide layer, and the oxide layer includes a thick region between thin regions on the bottom surface; removing the first spacers after selectively growing the oxide layer; implanting localized source and drain regions through the thin regions into the substrate using the thick region as an implant mask after removing the first spacers; removing the oxide layer after implanting the localized source and drain regions; forming a gate insulator on the bottom surface and second spacers on the sidewalls after removing the oxide layer; forming a gate electrode on the gate insulator and the second spacers, wherein the gate electrode is in the trench and spaced from and electrically isolated from the substrate; implanting sidewall source and drain regions through a top surface of the substrate; and forming a source and a drain in the substrate, wherein the source includes the localized source region adjacent to the bottom surface of the trench and the sidewall source region adjacent to the first sidewall, and the drain includes the localized drain region adjacent to the bottom surface of the trench and the sidewall drain region adjacent to the second sidewall.

Claim 41

A method of forming an IGFET, the method comprising the following steps in the sequence set forth: providing a semiconductor substrate of first conductivity type; patterning a photoresist layer with an opening over the substrate; applying an anisotropic etch through the opening in the photoresist layer to form a trench partially through the substrate, wherein the trench has first and second opposing sidewalls and a bottom surface; forming an oxide layer on the sidewalls and the bottom surface, wherein the oxide layer includes sidewall portions on the sidewalls, outer portions on the bottom surface and adjacent to the sidewall portions, and a central portion on the bottom surface between the outer portions; forming nitride spacers in the trench on the sidewall portions and the outer portions of the oxide layer, wherein the nitride spacers expose the central portion of the oxide layer; selectively growing the oxide layer by applying thermal oxidation, so that central portion of the oxide layer is thicker than the outer portions of the oxide layer, and the oxide layer includes a thick region between thin regions on the bottom surface; removing the nitride spacers; implanting localized source and drain regions through the thin regions into the substrate using the thick region as an implant mask; removing the oxide layer; forming second spacers on the sidewalls and on outer portions of the bottom surface, wherein the second spacers expose a central portion of the bottom surface between the outer portions of the bottom surface; growing a gate oxide on the central portion of the bottom surface; depositing polysilicon on the gate oxide and the second spacers; and polishing the polysilicon to form a polysilicon gate electrode in the trench and substantially aligned with a top surface of the substrate, wherein the polysilicon gate electrode is spaced from and electrically isolated from the substrate; wherein a source of second conductivity type in the substrate includes a sidewall source region merged with the localized source region, a drain of second conductivity type in the substrate includes a sidewall drain region merged with the localized drain region, the sidewall source region is adjacent to the first sidewall and extends between the top and bottom surfaces, the sidewall drain region is adjacent to the second sidewall and extends between the top and bottom surfaces, the localized source and drain regions are adjacent to the bottom surface of the trench, and the localized source and drain regions define a channel in the substrate adjacent to the central portion of the bottom surface of the trench.

Claim 42

A method of forming an IGFET, the method comprising the following steps in the sequence set forth: providing a semiconductor substrate of first conductivity type; patterning a photoresist layer with an opening over the substrate; applying an anisotropic etch through the opening in the photoresist layer to form a trench partially through the substrate, wherein the trench has first and second opposing sidewalls and a bottom surface; forming an oxide layer on the sidewalls and the bottom surface, wherein the oxide layer includes sidewall portions on the sidewalls, outer portions on the bottom surface and adjacent to the sidewall portions, and a central portion on the bottom surface between the outer portions; forming nitride spacers in the trench on the sidewall portions and the outer portions of the oxide layer, wherein the nitride spacers expose the central portion of the oxide layer; selectively growing the oxide layer by applying thermal oxidation, so that central portion of the oxide layer is thicker than the outer portions of the oxide layer, and the oxide layer includes a thick region between thin regions on the bottom surface; removing the nitride spacers; implanting localized source and drain regions through the thin regions into the substrate using the thick region as an implant mask; removing the oxide layer; forming second spacers on the sidewalls and on outer portions of the bottom surface, wherein the second spacers expose a central portion of the bottom surface between the outer portions of the bottom surface; growing a gate oxide on the central portion of the bottom surface; depositing polysilicon on the gate oxide and the second spacers; and polishing the polysilicon to form a polysilicon gate electrode in the trench and substantially aligned with a top surface of the substrate, wherein the polysilicon gate electrode is spaced from and electrically isolated from the substrate; wherein a source of second conductivity type in the substrate includes a sidewall source region merged with the localized source region, a drain of second conductivity type in the substrate includes a sidewall drain region merged with the localized drain region, the sidewall source region is adjacent to the first sidewall and extends between the top and bottom surfaces, the sidewall drain region is adjacent to the second sidewall and extends between the top and bottom surfaces, the localized source and drain regions are adjacent to the bottom surface of the trench, and the localized source and drain regions define a channel in the substrate adjacent to the central portion of the bottom surface of the trench.