Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls

Claim 1

A method for fabrication of a non-symmetrical IGFET comprising: (1) providing a semiconductor substrate; (2) forming an insulating film on the semiconductor substrate; (3) forming a gate material on the insulating film; (4) removing a first portion of the gate material overlying a first region of the semiconductor substrate to form a first sidewall of a gate electrode, wherein the first sidewall of the gate electrode is defined by a first masking film; (5) implanting a dopant into the first region after forming the first sidewall of the gate electrode; (6) removing a second portion of the gate material overlying a second region of the semiconductor substrate to form a second sidewall of the gate electrode after implanting the dopant into the first region, wherein the second sidewall of the gate electrode is defined by a second masking film that is formed after removing the first masking film; (7) implanting a dopant into the second region after forming the second sidewall of the gate electrode; (8) forming spacers adjacent to each of said first and second sidewalls of the gate electrode; and then (9) implanting a dopant into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers.

Claim 2

A method for fabrication of a non-symmetrical IGFET comprising: (1) providing a semiconductor substrate; (2) forming an insulating film on the semiconductor substrate; (3) forming a gate material on the insulating film; (4) removing a first portion of the gate material overlying a first region of the semiconductor substrate to form a first sidewall of a gate electrode, wherein the first sidewall of the gate electrode is defined by a first masking film; (5) implanting a dopant into the first region after forming the first sidewall of the gate electrode; (6) removing a second portion of the gate material overlying a second region of the semiconductor substrate to form a second sidewall of the gate electrode after implanting the dopant into the first region, wherein the second sidewall of the gate electrode is defined by a second masking film that is formed after removing the first masking film; (7) implanting a dopant into the second region after forming the second sidewall of the gate electrode; (8) forming spacers adjacent to each of said first and second sidewalls of the gate electrode; and then (9) implanting a dopant into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers.

Claim 20

A method for fabrication of a non-symmetrical IGFET comprising: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming a polysilicon layer on the gate oxide, wherein the polysilicon layer includes first and second portions; forming, over the top surface of said polysilicon layer, a first photoresist layer having an opening above the first portion of the polysilicon layer; etching the first portion of the polysilicon layer through the opening in said first photoresist layer to form a first sidewall of a gate electrode at a location defined by said first photoresist layer; removing said first photoresist layer; implanting a heavily doped source region into the semiconductor substrate and substantially aligned with the first sidewall of the gate electrode; forming, over the heavily doped source region, the first sidewall of the gate electrode and at least a part of the top surface of said polysilicon layer, a second photoresist layer having an opening above the second portion of the polysilicon layer; etching the second portion of the polysilicon layer through the opening in said second photoresist layer to form a second sidewall of the gate electrode at a location defined by said second photoresist layer; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the second sidewall of the gate electrode; removing said second photoresist layer after implanting the lightly doped drain region; depositing an oxide layer to cover the surface of the semiconductor substrate, the sidewalls of the gate electrode and the top surface of the gate electrode; removing said oxide layer from the top surface of said gate electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the gate electrode to form spacers adjacent to each of said first and second sidewalls of the gate electrode; and implanting a dopant into portions of the drain and source regions of the semiconductor substrate outside the gate electrode and the spacers and substantially aligned with the outside edges of said spacers, wherein a portion of the drain region is heavily doped and wherein the lightly doped drain region beneath the spacer adjacent to the second sidewall of the gate electrode is retained.

Claim 21

A method for fabrication of a non-symmetrical IGFET comprising: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming a polysilicon layer on the gate oxide, wherein the polysilicon layer includes first and second portions; forming, over the top surface of said polysilicon layer, a first photoresist layer having an opening above the first portion of the polysilicon layer; etching the first portion of the polysilicon layer through the opening in said first photoresist layer to form a first sidewall of a gate electrode at a location defined by said first photoresist layer; removing said first photoresist layer; implanting a heavily doped source region into the semiconductor substrate and substantially aligned with the first sidewall of the gate electrode; forming, over the heavily doped source region, the first sidewall of the gate electrode and at least a part of the top surface of said polysilicon layer, a second photoresist layer having an opening above the second portion of the polysilicon layer; etching the second portion of the polysilicon layer through the opening in said second photoresist layer to form a second sidewall of the gate electrode at a location defined by said second photoresist layer; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the second sidewall of the gate electrode; removing said second photoresist layer after implanting the lightly doped drain region; depositing an oxide layer to cover the surface of the semiconductor substrate, the sidewalls of the gate electrode and the top surface of the gate electrode; removing said oxide layer from the top surface of said gate electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the gate electrode to form spacers adjacent to each of said first and second sidewalls of the gate electrode; and implanting a dopant into portions of the drain and source regions of the semiconductor substrate outside the gate electrode and the spacers and substantially aligned with the outside edges of said spacers, wherein a portion of the drain region is heavily doped and wherein the lightly doped drain region beneath the spacer adjacent to the second sidewall of the gate electrode is retained.

Claim 24

A method for fabrication of a non-symmetrical IGFET comprising: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming a polysilicon layer on the gate oxide, wherein the polysilicon layer includes first and second portions; forming, over the top surface of said polysilicon layer, a first photoresist layer having an opening above the first portion of the polysilicon layer; etching the first portion of the polysilicon layer through the opening in said first photoresist layer to form a first sidewall of a gate electrode at a location defined by said first photoresist layer; removing said first photoresist layer; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the first sidewall of the gate electrode; forming, over the lightly doped drain region, the first sidewall of the gate electrode and at least a part of the top surface of said polysilicon layer, a second photoresist layer having an opening above the second portion of the polysilicon layer; etching the second portion of the polysilicon layer through the opening in said second photoresist layer to form a second sidewall of the gate electrode at a location defined by said second photoresist layer; implanting a heavily doped source region into the semiconductor substrate substantially aligned with the second sidewall of the gate electrode; removing said second photoresist layer after implanting the heavily doped source region; depositing an oxide layer to cover the surface of the semiconductor substrate, the sidewalls of the gate electrode and the top surface of the gate electrode; removing said oxide layer from the top surface of said gate electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the gate to form spacers adjacent to each of said first and second sidewalls of the gate electrode; and implanting a dopant into portions of the drain and source regions of the semiconductor substrate outside the gate electrode and the spacers and substantially aligned with the outside edges of said spacers, wherein a portion of the drain region is heavily doped and wherein the lightly doped drain region beneath the spacer adjacent to the first sidewall of the gate electrode is retained.

Claim 25

A method for fabrication of a non-symmetrical IGFET comprising: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming a polysilicon layer on the gate oxide, wherein the polysilicon layer includes first and second portions; forming, over the top surface of said polysilicon layer, a first photoresist layer having an opening above the first portion of the polysilicon layer; etching the first portion of the polysilicon layer through the opening in said first photoresist layer to form a first sidewall of a gate electrode at a location defined by said first photoresist layer; removing said first photoresist layer; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the first sidewall of the gate electrode; forming, over the lightly doped drain region, the first sidewall of the gate electrode and at least a part of the top surface of said polysilicon layer, a second photoresist layer having an opening above the second portion of the polysilicon layer; etching the second portion of the polysilicon layer through the opening in said second photoresist layer to form a second sidewall of the gate electrode at a location defined by said second photoresist layer; implanting a heavily doped source region into the semiconductor substrate substantially aligned with the second sidewall of the gate electrode; removing said second photoresist layer after implanting the heavily doped source region; depositing an oxide layer to cover the surface of the semiconductor substrate, the sidewalls of the gate electrode and the top surface of the gate electrode; removing said oxide layer from the top surface of said gate electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the gate to form spacers adjacent to each of said first and second sidewalls of the gate electrode; and implanting a dopant into portions of the drain and source regions of the semiconductor substrate outside the gate electrode and the spacers and substantially aligned with the outside edges of said spacers, wherein a portion of the drain region is heavily doped and wherein the lightly doped drain region beneath the spacer adjacent to the first sidewall of the gate electrode is retained.