US5801448A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Conductive lines on the back side of wafers and dice for semiconductor interconnects
Assignee: Micron Technology Inc
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Filing: 1997-04-30
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Granted: 1998-09-01
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Expires: 2017-04-30
Abstract
Abstract An apparatus and a method for increasing integrated circuit density comprising semiconductor wafers, wafer portions or dice ("semiconductor elements") having conductive traces on the back side thereof. These semiconductor elements are stacked such that the traces on the back side of an upper semiconductor become part of the interconnect traces of the semiconductor stacked below. The traces lead to one or more edges of the semiconductor element such that the traces can make electrical contact with an external substrate, leadframe, or wiring arrangement.
Inventors
- 👤 Michael B. Ball
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:29
CPC Classifications
H; H10; H10W; H10W90/00; H10W72/00; H10W72/01; H10W72/0198; H10W72/071; H10W72/072; H10W72/07251; H10W72/07254; H10W72/20; H10W72/241; H10W72/247; H10W72/29; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/834; H10W72/90; H10W72/941; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
73 words
A semiconductor configuration, comprising: a discrete semiconductor element having a first active exterior surface and a second opposing exterior surface; said first active exterior surface including integrated circuitry thereon with at least one flip chip connection protruding therefrom; and said second opposing exterior surface carrying at least one conductive trace extending thereover and including a contact area, wherein said at least one conductive trace lacks direct electrical communication with said discrete semiconductor element.
Claim 2
Dependent Claim
73 words
A semiconductor configuration, comprising: a discrete semiconductor element having a first active exterior surface and a second opposing exterior surface; said first active exterior surface including integrated circuitry thereon with at least one flip chip connection protruding therefrom; and said second opposing exterior surface carrying at least one conductive trace extending thereover and including a contact area, wherein said at least one conductive trace lacks direct electrical communication with said discrete semiconductor element.
Claim 3
Dependent Claim
25 words
The semiconductor configuration of claim 1, further comprising an insulative material disposed between the second opposing exterior surface and said at least one conductive trace.
Claim 4
Dependent Claim
16 words
The semiconductor configuration of claim 1, wherein said discrete semiconductor element is a singulated semiconductor die.
Claim 5
Dependent Claim
15 words
The semiconductor configuration of claim 1, wherein said discrete semiconductor element is a semiconductor wafer.
Claim 6
Dependent Claim
29 words
The semiconductor configuration of claim 1, wherein said discrete semiconductor element is a semiconductor wafer portion containing a plurality of semiconductor die locations in substantially mutual lateral coplanar relationship.
Claim 7
Dependent Claim
22 words
The semiconductor configuration of claim 1, wherein said at least one conductive trace extends to an edge of said discrete semiconductor element.
Claim 8
Dependent Claim
180 words
A semiconductor element stack configuration, comprising: a plurality of discrete semiconductor elements; said discrete semiconductor elements each having a first exterior surface and a second opposing exterior surface; at least one of said first exterior surfaces being an active surface including integrated circuitry thereon with at least one flip chip connection protruding therefrom; and at least one of said second opposing exterior surfaces carrying at least one conductive trace including a contact area, wherein said at least one conductive trace lacks direct electrical communication with said discrete semiconductor element upon which said at least one conductive trace is carried; said plurality of discrete semiconductor elements being aligned facing in the same direction, one abutting another such that said second opposing exterior surface of a first discrete semiconductor element carrying a conductive trace abuts said first exterior surface of a second semiconductor element including integrated circuitry and at least one flip chip connection, and the at least one flip chip connection of the second semiconductor element contacts the contact area of the first discrete semiconductor element adjacent the second semiconductor element.
Claim 9
Dependent Claim
180 words
A semiconductor element stack configuration, comprising: a plurality of discrete semiconductor elements; said discrete semiconductor elements each having a first exterior surface and a second opposing exterior surface; at least one of said first exterior surfaces being an active surface including integrated circuitry thereon with at least one flip chip connection protruding therefrom; and at least one of said second opposing exterior surfaces carrying at least one conductive trace including a contact area, wherein said at least one conductive trace lacks direct electrical communication with said discrete semiconductor element upon which said at least one conductive trace is carried; said plurality of discrete semiconductor elements being aligned facing in the same direction, one abutting another such that said second opposing exterior surface of a first discrete semiconductor element carrying a conductive trace abuts said first exterior surface of a second semiconductor element including integrated circuitry and at least one flip chip connection, and the at least one flip chip connection of the second semiconductor element contacts the contact area of the first discrete semiconductor element adjacent the second semiconductor element.
Claim 10
Dependent Claim
29 words
The semiconductor element stack configuration of claim 7, further comprising an insulative material disposed between each of the second opposing exterior surfaces and the at least one conductive trace.
Claim 11
Dependent Claim
22 words
The semiconductor element stack configuration of claim 7, wherein each of said plurality of discrete semiconductor elements is a single semiconductor die.
Claim 12
Dependent Claim
21 words
The semiconductor element stack configuration if claim 7, wherein each of said plurality of discrete semiconductor elements is a semiconductor wafer.
Claim 13
Dependent Claim
35 words
The semiconductor element stack configuration of claim 7, wherein each of said plurality of discrete semiconductor elements is a semiconductor wafer portion containing a plurality of semiconductor die locations in substantially mutual lateral coplanar relationship.
Claim 14
Dependent Claim
26 words
The semiconductor element stack configuration of claim 7, wherein said at least one conductive trace is routed to an edge of its respective discrete semiconductor element.
Claim 15
Dependent Claim
206 words
A semiconductor element assembly, comprising: a plurality of discrete semiconductor elements; said discrete semiconductor elements each having a first exterior surface and a second opposing exterior surface; at least one of said first exterior surfaces being an active surface including integrated circuitry thereon with at least one flip chip connection protruding therefrom; at least one of said second opposing exterior surfaces carrying at least one conductive trace having a contact area, wherein said at least one conductive trace lacks direct electrical communication with said discrete semiconductor element upon which said at least one conductive trace is carried; said plurality of discrete semiconductor elements being aligned facing in the same direction, one abutting another such that said second opposing exterior surface of a first discrete semiconductor element abuts said first exterior surface of a second semiconductor element, wherein the at least one flip chip connection of the second semiconductor element contacts the contact area of an adjacent first discrete semiconductor element; said at least one conductive trace is routed to an edge of its respective discrete semiconductor element and terminates to at least one external connection point; and a carrier substrate including at least one contact in electrical communication with said at least one external connection point.
Claim 16
Dependent Claim
206 words
A semiconductor element assembly, comprising: a plurality of discrete semiconductor elements; said discrete semiconductor elements each having a first exterior surface and a second opposing exterior surface; at least one of said first exterior surfaces being an active surface including integrated circuitry thereon with at least one flip chip connection protruding therefrom; at least one of said second opposing exterior surfaces carrying at least one conductive trace having a contact area, wherein said at least one conductive trace lacks direct electrical communication with said discrete semiconductor element upon which said at least one conductive trace is carried; said plurality of discrete semiconductor elements being aligned facing in the same direction, one abutting another such that said second opposing exterior surface of a first discrete semiconductor element abuts said first exterior surface of a second semiconductor element, wherein the at least one flip chip connection of the second semiconductor element contacts the contact area of an adjacent first discrete semiconductor element; said at least one conductive trace is routed to an edge of its respective discrete semiconductor element and terminates to at least one external connection point; and a carrier substrate including at least one contact in electrical communication with said at least one external connection point.
Claim 17
Dependent Claim
32 words
The semiconductor element assembly of claim 13, further comprising an insulative material disposed between said at least one second opposing exterior surface carrying at least one conductive trace and the conductive trace.
Claim 18
Dependent Claim
21 words
The semiconductor element assembly of claim 13, wherein each of said plurality of discrete semiconductor elements in a single semiconductor die.
Claim 19
Dependent Claim
20 words
The semiconductor element assembly of claim 13, wherein each of said plurality of discrete semiconductor elements is a semiconductor wafer.
Claim 20
Dependent Claim
34 words
The semiconductor element assembly of claim 13, wherein each of said plurality of discrete semiconductor elements is a semiconductor wafer portion containing a plurality of semiconductor die locations in substantially mutual lateral coplanar relationship.
Claim 21
Dependent Claim
39 words
The semiconductor element assembly of claim 13, wherein a plurality of semiconductor element second opposing exterior surfaces carries at least one conductive trace, each routed to an edge of that semiconductor element and terminating in an external connection point.
Claim 22
Dependent Claim
45 words
The semiconductor element assembly of claim 18, wherein said carrier substrate includes a plurality of contacts, at least one of said plurality of contacts contact in electrical communication with said at least one external connection point of each of said plurality of discrete semiconductor elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |