US5748546A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sensing scheme for flash memory with multilevel cells
Assignee: Intel Corp
•
Filing: 1997-04-10
•
Granted: 1998-05-05
•
Expires: 2017-04-10
Abstract
Abstract Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage Vt of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.
Inventors
- 👤 Mark E. Bauer
- 👤 Sanjay Talreja
- 👤 Kevin W. Frary
- 👤 Gregory Atwood
- 👤 Albert Fazio
- 👤 Johnny Javanifard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C2211/00; G11C2211/56; G11C2211/563; G11C2211/5632
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
346 words
In a flash memory device including at least one flash electrically-erasable programmable read-only memory (EEPROM) cell having n bits indicative of 2 n states, each state corresponding to a predetermined range of cell charge levels, a method for determining a state of the flash EEPROM cell, the method comprising the steps of: a) sensing a cell charge level of the flash EEPROM cell; b) comparing using a first comparator the cell charge level of the flash EEPROM cell and a reference cell charge level of a selected first reference cell; c) outputting from the first comparator a result of step b) indicative of a first one of the n bits in the flash EEPROM cell; d) supplying the result of step b) to an input of a selector circuit, the selector circuit selecting one of a second reference cell and a third reference cell, wherein selection between the second and third reference cells is done in response to the result of step b), the second reference cell being selected if the cell charge level of the flash EEPROM cell is less than the reference cell charge level of the selected first reference cell, and the third reference cell being selected if the cell charge level of the flash EEPROM cell is greater than the reference cell charge level of the selected first reference cell; e) comparing using a second comparator the cell charge level of the flash EEPROM cell to the selected one of a reference cell charge level of the second reference cell and a reference cell charge level of the third reference cell; and f) outputting from the second comparator a result of step e) indicative of a second one of the n bits of the flash EEPROM cell wherein the first comparator continues to output the result of step b) while steps d), e), and f) are performed such that the first comparator outputs the first one of the n bits and the second comparator outputs the second one of the n bits simultaneously to indicate the state of the flash EEPROM cell.
Claim 2
Dependent Claim
346 words
In a flash memory device including at least one flash electrically-erasable programmable read-only memory (EEPROM) cell having n bits indicative of 2 n states, each state corresponding to a predetermined range of cell charge levels, a method for determining a state of the flash EEPROM cell, the method comprising the steps of: a) sensing a cell charge level of the flash EEPROM cell; b) comparing using a first comparator the cell charge level of the flash EEPROM cell and a reference cell charge level of a selected first reference cell; c) outputting from the first comparator a result of step b) indicative of a first one of the n bits in the flash EEPROM cell; d) supplying the result of step b) to an input of a selector circuit, the selector circuit selecting one of a second reference cell and a third reference cell, wherein selection between the second and third reference cells is done in response to the result of step b), the second reference cell being selected if the cell charge level of the flash EEPROM cell is less than the reference cell charge level of the selected first reference cell, and the third reference cell being selected if the cell charge level of the flash EEPROM cell is greater than the reference cell charge level of the selected first reference cell; e) comparing using a second comparator the cell charge level of the flash EEPROM cell to the selected one of a reference cell charge level of the second reference cell and a reference cell charge level of the third reference cell; and f) outputting from the second comparator a result of step e) indicative of a second one of the n bits of the flash EEPROM cell wherein the first comparator continues to output the result of step b) while steps d), e), and f) are performed such that the first comparator outputs the first one of the n bits and the second comparator outputs the second one of the n bits simultaneously to indicate the state of the flash EEPROM cell.
Claim 3
Dependent Claim
192 words
The method as described in claim 1 further comprising the steps of: g) in response to a result of step f), selecting one of a fourth reference cell and a fifth reference cell, the fourth reference cell being selected if the cell charge level of the flash EEPROM cell is a first value and the fifth reference cell being selected if the cell charge level of the flash EEPROM cell is a second value; h) comparing the cell charge level of the flash EEPROM cell and a reference cell charge level of the selected one of the fourth and fifth reference cells; and i) outputting a result of step h) indicative of a third one of the n bits in the flash EEPROM cell wherein the first and second comparators continue to output the results of steps b) and f), respectively, while steps g), h), and i) are performed, such that the first comparator outputs the first one of the n bits and the second comparator outputs the second one of the n bits simultaneously with the third one of the n bits to indicate the state of the flash EEPROM cell.
Claim 4
Dependent Claim
300 words
In a flash memory device including at least one flash electrically-erasable programmable read-only memory (EEPROM) cell having n bits indicative of 2 n states, each state corresponding to a predetermined range of cell charge levels, a method for determining a state of the flash EEPROM cell, the method comprising the steps of: a) sensing a cell charge level of the flash EEPROM cell; b) comparing using a comparator the cell charge level of the flash EEPROM cell and a reference cell charge level of a selected first reference cell in a decode circuit; c) outputting from the comparator a result of step b) indicative of a first one of the n bits in the flash EEPROM cell; d) supplying the result of step b) to an input of the decode circuit, the decode circuit selecting one of a second reference cell and a third reference cell in response to the result of step b), the second reference cell being selected if the cell charge level of the flash EEPROM cell is less than the reference cell charge level of the selected first reference cell, and the third reference cell being selected if the cell charge level of the flash EEPROM cell is greater than the reference cell charge level of the selected first reference cell; e) comparing using the comparator the cell charge level of the flash EEPROM cell to the selected one of a reference cell charge level of the second reference cell and a reference cell charge level of the third reference cell; and f) outputting from the comparator a result of step e) indicative of a second one of the n bits of the flash EEPROM cell wherein the result of step b) and the result of step e) indicate the state of the flash EEPROM cell.
Claim 5
Dependent Claim
300 words
In a flash memory device including at least one flash electrically-erasable programmable read-only memory (EEPROM) cell having n bits indicative of 2 n states, each state corresponding to a predetermined range of cell charge levels, a method for determining a state of the flash EEPROM cell, the method comprising the steps of: a) sensing a cell charge level of the flash EEPROM cell; b) comparing using a comparator the cell charge level of the flash EEPROM cell and a reference cell charge level of a selected first reference cell in a decode circuit; c) outputting from the comparator a result of step b) indicative of a first one of the n bits in the flash EEPROM cell; d) supplying the result of step b) to an input of the decode circuit, the decode circuit selecting one of a second reference cell and a third reference cell in response to the result of step b), the second reference cell being selected if the cell charge level of the flash EEPROM cell is less than the reference cell charge level of the selected first reference cell, and the third reference cell being selected if the cell charge level of the flash EEPROM cell is greater than the reference cell charge level of the selected first reference cell; e) comparing using the comparator the cell charge level of the flash EEPROM cell to the selected one of a reference cell charge level of the second reference cell and a reference cell charge level of the third reference cell; and f) outputting from the comparator a result of step e) indicative of a second one of the n bits of the flash EEPROM cell wherein the result of step b) and the result of step e) indicate the state of the flash EEPROM cell.
References Cited (Backward Citations)
US3142824A
Cited
DE1486912A1
Cited
US3505655A
Cited
FR2246022A1
Cited
US4181980A
Cited
US4202044A
Cited
US4287570A
Cited
US4357685A
Cited
JPS5660247A
Cited
US4415992A
Cited
US4388702A
Cited
US4460982A
Cited
US4586163A
Cited
EP0130614A2
Cited
US4653023A
Cited
US4771404A
Cited
US4701884A
Cited
US5012448A
Cited
US4943948A
Cited
US5034922A
Cited
US4875188A
Cited
US5053990A
Cited
US5222046A
Cited
EP0349775A2
Cited
US5043940A
Cited
US5293560A
Cited
US5095344A
Cited
US4989179A
Cited
US4890259A
Cited
US5262984A
Cited
US5172338B1
Cited
US5163021A
Cited
US5172338A
Cited
US5297148A
Cited
WO1990012400A1
Cited
US5394359A
Cited
EP0409697A1
Cited
US5200920A
Cited
US5289406A
Cited
US5126967A
Cited
US5260901A
Cited
US5351210A
Cited
WO1992012519A1
Cited
US5218569A
Cited
US5513333A
Cited
US5463757A
Cited
US5448712A
Cited
US5287305A
Cited
US5361343A
Cited
US5305273A
Cited
US5237535A
Cited
US5388064A
Cited
US5289412A
Cited
US5283761A
Cited
US5375097A
Cited
US5537350A
Cited
US5440505A
Cited
US5566125A
Cited
US5450363A
Cited
US5539690A
Cited
US5515317A
Cited
US5497354A
Cited
US5594691A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |