Patent US5729503A successfully refreshed from Google Patents.
US5729503A
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Address transition detection on a synchronous design
Assignee: Round Rock Research LLC
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Filing: 1995-07-24
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Granted: 1998-03-17
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Expires: 2015-07-24
Abstract
Abstract An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit. The address transition detection circuit generates an equilibration control signal between memory access cycles.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:28
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1024; G11C7/1039; G11C7/1045; G11C7/1078; G11C7/109; G11C7/1096; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
143 words
A circuit comprising: an address buffer providing a first address; an input adapted to receive an access cycle strobe signal; a memory array; an address generator coupled to said address buffer and to said input, said address generator adapted to provide a series of addresses in response to receipt of the first address and receipt of the access cycle strobe signal; and an address transition detection circuit coupled to said address buffer and to said address generator, said address transition detection circuit having an output coupled to said memory array, providing a first equilibration signal to said memory array in response to the first address in a first mode of operation, and said address transition detection circuit providing a second equilibration signal to said memory array in response to each subsequent address of the series of addresses in a second mode of operation.
Claim 2
Dependent Claim
143 words
A circuit comprising: an address buffer providing a first address; an input adapted to receive an access cycle strobe signal; a memory array; an address generator coupled to said address buffer and to said input, said address generator adapted to provide a series of addresses in response to receipt of the first address and receipt of the access cycle strobe signal; and an address transition detection circuit coupled to said address buffer and to said address generator, said address transition detection circuit having an output coupled to said memory array, providing a first equilibration signal to said memory array in response to the first address in a first mode of operation, and said address transition detection circuit providing a second equilibration signal to said memory array in response to each subsequent address of the series of addresses in a second mode of operation.
Claim 3
Dependent Claim
16 words
The circuit of claim 1 further comprising: a mode select circuit coupled to said address generator.
Claim 4
Dependent Claim
18 words
The circuit of claim 1 wherein said memory array comprises a plurality of dynamic random access memory elements.
Claim 5
Dependent Claim
42 words
The circuit of claim 1 further comprising: a pair of complimentary data lines coupled to said memory array; and an equilibration circuit coupled to said complimentary data lines, responsive to the first or second equilibration signal to equilibrate said complimentary data lines.
Claim 6
Dependent Claim
92 words
A circuit comprising: a memory array comprising a plurality of rows and a plurality of columns; a column address generator, operable in a burst mode and a page mode, coupled to said memory array; a mode select circuit coupled to said column address generator to select the burst mode or the page mode; an address transition detection circuit coupled to said column address generator; a pair of complimentary data lines coupled to said memory array; and an equilibration circuit coupled to said complimentary data lines and to said address transition detection circuit.
Claim 7
Dependent Claim
92 words
A circuit comprising: a memory array comprising a plurality of rows and a plurality of columns; a column address generator, operable in a burst mode and a page mode, coupled to said memory array; a mode select circuit coupled to said column address generator to select the burst mode or the page mode; an address transition detection circuit coupled to said column address generator; a pair of complimentary data lines coupled to said memory array; and an equilibration circuit coupled to said complimentary data lines and to said address transition detection circuit.
Claim 8
Dependent Claim
66 words
A circuit comprising: an address generator responsive to a first polarity of transitions of a control signal to provide a series of addresses; an address latch responsive to a second polarity of transitions of the control signal to latch each of the series of addresses; and an address transition detection circuit responsive to the latched addresses, said address transition detection circuit providing an equilibration control signal.
Claim 9
Dependent Claim
66 words
A circuit comprising: an address generator responsive to a first polarity of transitions of a control signal to provide a series of addresses; an address latch responsive to a second polarity of transitions of the control signal to latch each of the series of addresses; and an address transition detection circuit responsive to the latched addresses, said address transition detection circuit providing an equilibration control signal.
Claim 10
Independent Claim
66 words
A method of operating a memory device having an address generation circuit, comprising steps of: receiving an address from a source external to the memory device; latching the address; generating a next address in the address generation circuit; latching the next address; detecting a difference between the address and the next address; and generating an equilibration signal in response to said step of detecting a difference.
Claim 11
Independent Claim
66 words
A method of operating a memory device having an address generation circuit, comprising steps of: receiving an address from a source external to the memory device; latching the address; generating a next address in the address generation circuit; latching the next address; detecting a difference between the address and the next address; and generating an equilibration signal in response to said step of detecting a difference.
Claim 12
Independent Claim
89 words
A method of supplying data to a microprocessor comprising steps of: addressing a memory circuit with an address from the microprocessor; latching the address within the memory circuit; generating a next address within the memory circuit; detecting a difference between the address and the next address; generating an equilibration signal within the memory circuit in response to said step of detecting a difference; supplying data to the microprocessor from the address of the memory circuit; and supplying data to the microprocessor from the next address of the memory circuit.
Claim 13
Independent Claim
89 words
A method of supplying data to a microprocessor comprising steps of: addressing a memory circuit with an address from the microprocessor; latching the address within the memory circuit; generating a next address within the memory circuit; detecting a difference between the address and the next address; generating an equilibration signal within the memory circuit in response to said step of detecting a difference; supplying data to the microprocessor from the address of the memory circuit; and supplying data to the microprocessor from the next address of the memory circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-16 | 2001-09-15 | 2002-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-16 | 2005-09-15 | 2006-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-16 | 2009-09-15 | 2010-03-17 | $7700.00 | Window Closed / Lapsed |