US5712816A — Method for evaluating the dielectric layer of non…

Claim 1

Independent Claim 207 words

A method of evaluating a dielectric layer of a plurality of cells of one of a nonvolatile EPROM, EEPROM and flash-EEPROM memory array, the plurality of cells being arranged in a plurality of rows and a plurality of columns, each cell having a drain, a source and a gate, the method comprising the steps of: connecting the drain of each of the plurality of cells together such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, the source of each of the plurality of cells together such that a source of the first cell is un-interruptibly connected to a source of the second cell, and the gate of each of the plurality of cells together such that a gate of the first cell is un-interruptibly connected to a gate of the second cell, applying to said plurality of cells a stress to extract electrons from floating gate regions of defective cells of said memory array, wherein said stress is less than a tunneling stress required to cause Fowler-Nordheim tunneling in a non-defective cell, and subsequently measuring a characteristic of said plurality of cells.

Claim 2

Independent Claim 207 words

A method of evaluating a dielectric layer of a plurality of cells of one of a nonvolatile EPROM, EEPROM and flash-EEPROM memory array, the plurality of cells being arranged in a plurality of rows and a plurality of columns, each cell having a drain, a source and a gate, the method comprising the steps of: connecting the drain of each of the plurality of cells together such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, the source of each of the plurality of cells together such that a source of the first cell is un-interruptibly connected to a source of the second cell, and the gate of each of the plurality of cells together such that a gate of the first cell is un-interruptibly connected to a gate of the second cell, applying to said plurality of cells a stress to extract electrons from floating gate regions of defective cells of said memory array, wherein said stress is less than a tunneling stress required to cause Fowler-Nordheim tunneling in a non-defective cell, and subsequently measuring a characteristic of said plurality of cells.

Claim 3

Dependent Claim 22 words

A method as claimed in claim 1, wherein said step of applying a stress comprises the step of applying an electrical stress.

Claim 4

Dependent Claim 35 words

A method as claimed in claim 1, wherein said step of measuring the characteristic comprises the step of applying to said cells a voltage lower than a standard threshold voltage of a non-defective memory cell.

Claim 5

Dependent Claim 14 words

A method as claimed in claim 3, wherein said voltage is a gate voltage.

Claim 6

Dependent Claim 24 words

A method as claimed in claim 1, wherein said step of measuring the characteristic comprises the step of measuring drain current of said cells.

Claim 7

Dependent Claim 25 words

A method as claimed in claim 1, wherein said step of measuring the characteristic comprises the step of measuring a source current of said cells.

Claim 8

Dependent Claim 24 words

A method as claimed in claim 1, wherein said step of measuring the characteristic comprises the step of measuring a transconductance of said cells.

Claim 9

Dependent Claim 30 words

A method as claimed in claim 1, wherein said method of applying a stress comprises the step of applying to said cells a stress voltage for a predetermined time interval.

Claim 10

Dependent Claim 59 words

A method as claimed in claim 8, for evaluating a gate oxide layer of a test cell, wherein said step of applying a stress voltage comprises the step of applying a stress voltage lower than a tunneling voltage of standard non-defective memory cells and greater than a tunneling voltage of a memory cell having a defective gate oxide layer.

Claim 11

Dependent Claim 38 words

A method as claimed in claim 9, wherein said step of applying a stress voltage comprises the step of applying a negative voltage to a gate region with respect to drain regions and source regions of said cells.

Claim 12

Dependent Claim 38 words

A method as claimed in claim 9, wherein said step of applying a stress voltage comprises the step of applying a positive voltage to a source region with respect to a substrate and gate regions of said cells.

Claim 13

Dependent Claim 57 words

A method as claimed in claim 8, for evaluating an interpoly dielectric layer interposed between a control gate region and a floating gate region of said cells, wherein said step of applying a stress voltage comprises the step of applying a positive voltage to said control gate region with respect to a substrate region of said cells.

Claim 14

Dependent Claim 28 words

A method as claimed in claim 8, wherein said step of applying a stress voltage comprises the step of applying a constant voltage for a given time interval.

Claim 15

Dependent Claim 30 words

A method as claimed in claim 8, wherein said step of applying a stress voltage comprises the step of applying a voltage increasing from a minimum to a maximum value.

Claim 16

Dependent Claim 15 words

A method as claimed in claim 14, wherein said increasing voltage is increased in steps.

Claim 17

Dependent Claim 52 words

A method as claimed in claim 15, wherein the method comprises a number of stress and measuring cycles, each cycle including applying said stress voltage and measuring the characteristic of said cells; the stress voltage in each cycle being increased by a predetermined amount as compared with that of a previous cycle.

Claim 18

Dependent Claim 38 words

A method as claimed in claim 1, further comprising an initial step of measuring the characteristic of said cells prior to applying said stress, and the step of comparing said characteristic measured before and after applying said stress.

Claim 19

Dependent Claim 28 words

A method as claimed in claim 17, further comprising the step of UV erasing said cells prior to said initial step of measuring the characteristic of said cells.

Claim 20

Dependent Claim 63 words

A method as claimed in claim 1, wherein said memory array comprises a test structure including an array of test cells having drain regions connected electrically to one another and to a single drain pad; source regions connected electrically to one another and to a single source pad; and control gate regions connected electrically to one another and to a single gate pad.

Claim 21

Dependent Claim 187 words

A test structure for testing one of a nonvolatile EPROM, EEPROM and flash-EEPROM memory, comprising: a plurality of cells arranged into a plurality of rows and a plurality of columns, so that a first cell is arranged in a first row and a first column, and a second cell is arranged in a second row and a second column, wherein the first cell includes a first drain region, a first source region, and a first gate region, and wherein the second cell includes a second drain region, a second source region, and a second gate region; a drain pad; non-switchable drain lines that un-interruptibly connect the first drain region of the first cell, the second drain region of the second cell, and the drain pad together; a source pad; non-switchable source lines that un-interruptibly connect the first source region of the first cell, the second source region of the second cell, and the source pad together; a gate pad; and non-switchable gate lines that un-interruptibly connect the first gate region of the first cell, the second gate region of the second cell, and the gate pad together.

Claim 22

Dependent Claim 187 words

A test structure for testing one of a nonvolatile EPROM, EEPROM and flash-EEPROM memory, comprising: a plurality of cells arranged into a plurality of rows and a plurality of columns, so that a first cell is arranged in a first row and a first column, and a second cell is arranged in a second row and a second column, wherein the first cell includes a first drain region, a first source region, and a first gate region, and wherein the second cell includes a second drain region, a second source region, and a second gate region; a drain pad; non-switchable drain lines that un-interruptibly connect the first drain region of the first cell, the second drain region of the second cell, and the drain pad together; a source pad; non-switchable source lines that un-interruptibly connect the first source region of the first cell, the second source region of the second cell, and the source pad together; a gate pad; and non-switchable gate lines that un-interruptibly connect the first gate region of the first cell, the second gate region of the second cell, and the gate pad together.

Claim 23

Dependent Claim 21 words

The test structure of claim 20, wherein each of the drain lines, the source lines, and the gate lines are metallic.

Claim 24

Dependent Claim 29 words

The test structure of claim 20, wherein each of the drain pad, the source pad, and the gate pad is metallic and constructed and arranged to permit external access.

Claim 25

Independent Claim 196 words

A method for evaluating a dielectric layer of a plurality of cells of a memory array, the plurality of cells including a plurality of rows and a plurality of columns such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, a source of the first cell is un-interruptibly connected to a source of the second cell, and a gate of the first cell is un-interruptibly connected to a gate of the second cell, the drains, sources and gates of the plurality of cells being connected together through respective un-interruptible connections, the method comprising the steps of: applying an electrical stress through the respective un-interruptible connections to the plurality of cells simultaneously, wherein the stress is sufficient to extract electrons from a floating gate region of a defective cell of the memory array, and wherein the stress is insufficient to cause Fowler-Nordheim tunneling in a non-defective cell of the memory array; and measuring a characteristic of the cells, quality of the dielectric layer of the cells being determined according to the measured characteristic.

Claim 26

Independent Claim 196 words

A method for evaluating a dielectric layer of a plurality of cells of a memory array, the plurality of cells including a plurality of rows and a plurality of columns such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, a source of the first cell is un-interruptibly connected to a source of the second cell, and a gate of the first cell is un-interruptibly connected to a gate of the second cell, the drains, sources and gates of the plurality of cells being connected together through respective un-interruptible connections, the method comprising the steps of: applying an electrical stress through the respective un-interruptible connections to the plurality of cells simultaneously, wherein the stress is sufficient to extract electrons from a floating gate region of a defective cell of the memory array, and wherein the stress is insufficient to cause Fowler-Nordheim tunneling in a non-defective cell of the memory array; and measuring a characteristic of the cells, quality of the dielectric layer of the cells being determined according to the measured characteristic.

Claim 27

Dependent Claim 39 words

The method of claim 23, wherein the step of applying includes the step of electrically biasing each cell through a plurality of non-switchable metal lines contacting each cell, the plurality of non-switchable metal lines being the respective un-interruptible connections.

Claim 28

Dependent Claim 35 words

The method of claim 24, wherein the step of electrically biasing includes the step of providing voltages from an external voltage source to a plurality of separate pads coupled to the plurality of metal lines.

Claim 29

Dependent Claim 50 words

The method of claim 23, wherein the step of measuring the characteristic includes the step of: measuring an aggregate source current of the memory array as a function of a gate voltage applied to the gate of each cell to determine whether the memory array includes a defective memory cell.

Claim 30

Dependent Claim 50 words

The method of claim 23, wherein the step of measuring the characteristic includes the step of: measuring an aggregate drain current of the memory array as a function of a gate voltage applied to the gate of each cell to determine whether the memory array includes a defective memory cell.

Claim 31

Dependent Claim 47 words

The method of claim 23, wherein the step of measuring the characteristic includes the step of: measuring transconductance of the memory array as a function of a gate voltage applied to the gate of each cell to determine the number of defective cells in the memory array.

Claim 32

Independent Claim 199 words

A system for evaluating a dielectric layer of a plurality of cells of a memory array, the plurality of cells including a plurality of rows and a plurality of columns such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, a source of the first cell is un-interruptibly connected to a source of the second cell, and a gate of the first cell is un-interruptibly connected to a gate of the second cell, the drains, sources and gates of the plurality of cells being connected together through respective un-interruptible connections, the system comprising: means for applying an electrical stress through the respective un-interruptible connections to the plurality of cells simultaneously, wherein the stress is sufficient to extract electrons from a floating gate region of a defective cell of the memory array, and wherein the stress is insufficient to cause Fowler-Nordheim tunneling in a non-defective cell of the memory array; and a measuring circuit that measures a characteristic of the cells, quality of the dielectric layer of the cells being determined according to the measured characteristic.

Claim 33

Independent Claim 199 words

A system for evaluating a dielectric layer of a plurality of cells of a memory array, the plurality of cells including a plurality of rows and a plurality of columns such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, a source of the first cell is un-interruptibly connected to a source of the second cell, and a gate of the first cell is un-interruptibly connected to a gate of the second cell, the drains, sources and gates of the plurality of cells being connected together through respective un-interruptible connections, the system comprising: means for applying an electrical stress through the respective un-interruptible connections to the plurality of cells simultaneously, wherein the stress is sufficient to extract electrons from a floating gate region of a defective cell of the memory array, and wherein the stress is insufficient to cause Fowler-Nordheim tunneling in a non-defective cell of the memory array; and a measuring circuit that measures a characteristic of the cells, quality of the dielectric layer of the cells being determined according to the measured characteristic.

Claim 34

Dependent Claim 38 words

The system of claim 29, wherein the means for applying includes means for electrically biasing each cell through a plurality of non-switchable metal lines contacting each cell, the plurality of non-switchable metal lines being the respective un-interruptible connections.

Claim 35

Dependent Claim 34 words

The system of claim 30, wherein the means for electrically biasing includes means for providing voltages from an external voltage source to a plurality of separate pads coupled to the plurality of metal lines.

Claim 36

Dependent Claim 46 words

The system of claim 29, wherein the measuring circuit includes: circuitry that measures an aggregate source current of the memory array as a function of a gate voltage applied to the gate of each cell to determine whether the memory array includes a defective memory cell.

Claim 37

Dependent Claim 46 words

The system of claim 29, wherein the measuring circuit includes: circuitry that measures an aggregate drain current of the memory array as a function of a gate voltage applied to the gate of each cell to determine whether the memory array includes a defective memory cell.

Claim 38

Dependent Claim 43 words

The system of claim 29, wherein the measuring circuit includes: circuitry that measures transconductance of the memory array as a function of a gate voltage applied to the gate of each cell to determine the number of defective cells in the memory array.

Claim 39

Independent Claim 182 words

A system for evaluating a dielectric layer of a plurality of cells of a memory array, the plurality of cells including a plurality of rows and a plurality of columns such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, a source of the first cell is un-interruptibly connected to a source of the second cell, and a gate of the first cell is un-interruptibly connected to a gate of the second cell, the system comprising: a plurality of un-interruptible connection structures that provide an electrical stress to the plurality of cells simultaneously, wherein the stress is sufficient to extract electrons from a floating gate region of a defective cell of the memory array, and wherein the stress is insufficient to cause Fowler-Nordheim tunneling in a non-defective cell of the memory array; and a measuring circuit that measures a characteristic of the cells, quality of the dielectric layer of the cells being determined according to the measured characteristic.

Claim 40

Independent Claim 182 words

A system for evaluating a dielectric layer of a plurality of cells of a memory array, the plurality of cells including a plurality of rows and a plurality of columns such that a drain of a first cell of a first row and a first column is un-interruptibly connected to a drain of a second cell of a second row and a second column, a source of the first cell is un-interruptibly connected to a source of the second cell, and a gate of the first cell is un-interruptibly connected to a gate of the second cell, the system comprising: a plurality of un-interruptible connection structures that provide an electrical stress to the plurality of cells simultaneously, wherein the stress is sufficient to extract electrons from a floating gate region of a defective cell of the memory array, and wherein the stress is insufficient to cause Fowler-Nordheim tunneling in a non-defective cell of the memory array; and a measuring circuit that measures a characteristic of the cells, quality of the dielectric layer of the cells being determined according to the measured characteristic.

Claim 41

Dependent Claim 30 words

The system of claim 35, wherein the plurality of un-interruptible connection structures includes a plurality of non-switchable metallic lines contacting each cell that provide electrical biasing voltages to each cell.

Claim 42

Dependent Claim 24 words

The system of claim 36, wherein the plurality of connection structures includes a plurality of separate pads coupled to the plurality of metal lines.

Claim 43

Dependent Claim 46 words

The system of claim 35, wherein the measuring circuit includes: circuitry that measures an aggregate source current of the memory array as a function of a gate voltage applied to the gate of each cell to determine whether the memory array includes a defective memory cell.

Claim 44

Dependent Claim 46 words

The system of claim 35, wherein the measuring circuit includes: circuitry that measures an aggregate drain current of the memory array as a function of a gate voltage applied to the gate of each cell to determine whether the memory array includes a defective memory cell.

Claim 45

Dependent Claim 43 words

The system of claim 35, wherein the measuring circuit includes: circuitry that measures transconductance of the memory array as a function of a gate voltage applied to the gate of each cell to determine the number of defective cells in the memory array.

Claim 46

Dependent Claim 25 words

The system of claim 35, further including an external power source, and wherein the electrical stress is a voltage provided by the external power source.

Claim 47

Dependent Claim 235 words

A test structure for testing one of a nonvolatile EPROM, EEPROM and flash-EEPROM memory, comprising: a drain pad; a source pad; a gate pad; a plurality of cells arranged in an array of rows and columns, the plurality of cells including: a first cell arranged in a first row and a first column of the array, wherein the first cell has a first drain, a first source and a first gate, and a second cell arranged in a second row and a second column of the array, wherein the second cell has a second drain, a second source and a second gate; an un-interruptible drain line un-interruptibly connected to the drain pad, the first drain, and the second drain together such that, when a drain signal is received by the drain pad, the drain signal is applied simultaneously to the first drain and the second drain; an un-interruptible source line un-interruptibly connected to the source pad, the first source, and the second source together which that, when a source signal is received by the source pad, the source signal is applied simultaneously to the first source and the second source; and an un-interruptible gate line un-interruptibly connected to the gate pad, the first gate, and the second gate together such that, when a gate signal is received by the gate pad, the gate signal is applied simultaneously to the first gate and the second gate.

Claim 48

Dependent Claim 235 words

A test structure for testing one of a nonvolatile EPROM, EEPROM and flash-EEPROM memory, comprising: a drain pad; a source pad; a gate pad; a plurality of cells arranged in an array of rows and columns, the plurality of cells including: a first cell arranged in a first row and a first column of the array, wherein the first cell has a first drain, a first source and a first gate, and a second cell arranged in a second row and a second column of the array, wherein the second cell has a second drain, a second source and a second gate; an un-interruptible drain line un-interruptibly connected to the drain pad, the first drain, and the second drain together such that, when a drain signal is received by the drain pad, the drain signal is applied simultaneously to the first drain and the second drain; an un-interruptible source line un-interruptibly connected to the source pad, the first source, and the second source together which that, when a source signal is received by the source pad, the source signal is applied simultaneously to the first source and the second source; and an un-interruptible gate line un-interruptibly connected to the gate pad, the first gate, and the second gate together such that, when a gate signal is received by the gate pad, the gate signal is applied simultaneously to the first gate and the second gate.

Claim 49

Dependent Claim 30 words

The test structure of claim 42, wherein each of the drain line, the source line, and the gate line is a hardwired metallic line that provides a non-switchable conduction path.

Claim 50

Dependent Claim 30 words

The test structure of claim 42, wherein each of the drain line, the source line, and the gate line is formed by un-interrupted uniform conducting material in a semiconductor structure.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-01-26	2001-07-28	2002-01-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-01-26	2005-07-28	2006-01-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-01-26	2009-07-28	2010-01-27	$7700.00	Window Closed / Lapsed

Method for evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories

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